There are 5 reset types in the AM26x SoC.
3 resets are restricted to R5F CPUs or R5FSS only.
Local Reset (L_RST) will reset only the R5F core, including the cache, MPU, and PMU.
Writing into R5SSx_COREy_LRST_CTRL register will reset the CPU. If the MSS_RCM_R5SSx_RST_WFICHECK_EN_R5_COREy is enabled then after the CPU enters the WFI, the CPU will give wfi signal to RCM to assert the L_RST. Make sure to unlock the MMR.
Global Reset (G_RST) will reset only the R5F core. Like L_RST, it will reset the cache, MPU, PMU, and the VIM config for the CPU.
Writing into R5SSx_COREy_GRST_CTRL register will reset the CPU. If the MSS_RCM_R5SSx_RST_WFICHECK_EN_R5_COREy is enabled then after the CPU enters the WFI, the CPU will give wfi signal to RCM to assert the G_RST. Make sure to unlock the MMR.
For AM263Px, the IPs which are R5SS dependent i.e. TMU, RAT, RL2 and FLC will also reset over G_RESET.
Note: The VIM RAM is not reset by the G_RST.
FSM Trigger (Cluster Reset) will reset both CPUs in the cluster. In addition to the CPU, it will reset components impacted by G_RST, debug/trace modules like ETM, CTI, CTM, and the lockstep module, i.e., CCM.
Writing into MSS_CTRL_R5SSx_CONTROL_RESET_FSM_TRIGGER register will reset the CPU.
If the MSS_RCM_R5SSx_RST_WFICHECK_EN_R5_CORE0 and MSS_RCM_R5SSx_RST_WFICHECK_EN_R5_CORE1 is enabled then after both the CPUs enters the WFI, then CPU will give wfi signal to RCM to assert the Cluster Reset. Make sure to unlock the MMR and only after both the CPUs enter WFI, the reset is asserted.
2 SoC-level resets. i.e. Warm Reset and POR (Cold Reset)
The warm reset and cold reset work equivalently for most IPs and will assert a standard reset.
| AM263x | AM263Px |
| R5SS0 | R5SS0 |
| R5SS1 | R5SS1 |
| DebugSS | DebugSS |
| EDMA | EDMA |
| MSS-INFRA (Interconnect bridges etc.) | MSS-INFRA (Interconnect bridges etc) |
| DCC(0-3) | DCC(0-3) |
| GPIO(1-4) | GPIO(1-4) |
| MCRC | MCRC |
| TOP_ESM | TOP_ESM |
| SPI(0-4) | SPI(0-7) |
| I2C(0-3) | I2C(0-3) |
| MCAN(0-3) | MCAN(0-7) |
| QSPI | OSPI |
| RTI(0-3) | RTI(0-7) |
| WDT(0-3) | WDT(0-3) |
| UART(0-5) | UART(0-5) |
| LIN(0-4) | LIN(0-4) |
| CPSW | CPSW |
| ICSS | ICSS |
| MMC0 | MMC0 |
| SPINLOCK0 | SPINLOCK0 |
| GPMC | -- |
| ELM | -- |
| HSM | HSM |
| EPMW(0-31) | EPMW(0-31) |
| ECAP(0-15) | ECAP(0-19) |
| EQEP(0-2) | EQEP(0-2) |
| SDFM(0-1) | SDFM(0-1) |
| CMPSSA(0-9) | CMPSSA(0-9) |
| CMPSSB(0-9) | CMPSSB(0-9) |
| ADC(0-4) | ADC(0-4) |
| DAC | ADC_R(0-1) |
| DAC | |
| ADC_SCTILE(0-11) | |
| ADC_AGG | |
| HW_RESOLVER |
There are some exceptions to these SoC-level resets.
| Tempsensor | Only resets on POR so that it can be used as a Warm Reset source. |
| TOP_CTRL registers related to Tempsensor | Only resets on POR so that it can be used as a Warm Reset source. |
| TOP_RCM registers related to warm reset cause | Only reset on POR. |
| MSS_RCM registers related to reset cause | Only reset on POR. |
As HSMSS is reseted as part of Warm Reset and Cold Reset (POR), the boot flow w.r.t Warm Reset and Cold Reset remains the same.
