Other Parts Discussed in Thread: TMDS243EVM
Tool/software:
Hello,
While looking at memory latencies in AM243x (SPRACV1B), I noticed DDR4 access time is unexpectedly high (and experiments with the TMDS243EVM confirmed this). As this document also mentions access time for "TCM of another Cortex-R5F" and I would like to minimize DDR4 usage, I would like to know if it is possible for one core to use the TCM of all other cores even if the cores themselves are not active.
Best regards,
Ricardo