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Tool/software:
Hi all,
I am using the TMS570LC4357 processor and Code is generated by HalCOGen. I want to detect single bit error on RAM / Flash.
If I understand the documentation than I have to call function "epcEnableSERREvent" (generated by HalCOGen) which sets the SERRENA bit in register EPCCNTRL to 0xA.
Than I have to activate the ESM low interrupt (ESM high is set by default) and the ESM channel 4 (EPC CERR).
Is that the way how it works ? And any idea how to test ?
Best regards
Lars Guenther
Hi Lars Guenther,
Can you please refer below thread once:
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Thanks & regards,
Jagadish.
Thanks, I will try.
But first of all, could you agree that the sequence in SW to detect signale error event is the following one:
- call of "epcEnableSERREvent" (generated by HalCOGen)
- activate corresponding ESM channel (4)
- and activate ESM low interrupt
Best regards
Lars
Hi Lars,
Your flow looks correct.
The ECC verification in this device will always be in enabled state the only thing is that we need to enable the corresponding interrupts.
For more details about injecting ECC error, you can refer the thread that i shared to you.
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Thanks & regards,
Jagadish.