RAM ECC Testing

Bindu Tanguturi

Other Parts Discussed in Thread: HALCOGEN

Devlopement Environment : Processor : TMS570LS20216 (Cortex R4), Code Composer Studio : 4.2.0.10018, TMS470 C/C++ CODE GENERATION TOOLS 4.6.3

I am working on the code for ECC RAM check. I have read the similar posts related to RAM ECC check and the SPNA126.pdf application note. I am little confused after reading the posts and the application note. I am not able to test the RAM ECC logic. Below are my queries.

1. In some posts, it was mentioned that SPNA126.pdf need some updations in documentation. Where can i get the latest version of SPNA126.pdf ?

2. The intial driver code that i am using is from the HALcogen. I assume that _memoryInit_ asm function intializes the entire RAM memory to zero. This is same as step1 mentioned in the section 3.4 of SPNA126.pdf. Is that correct ?

3. The sample code available for the RAM ECC testing is for the CCS version 3. Is there any sample code available for the above development enviroment mentioned ?

4. In the application note, step 3 of section 3.4 is as below ." write data to specific RAM location" . But i understand that RAM ECC checking will be done by corrupting ECC bits not the RAM memory. Is that my understanding correct ? If so let me know how to corrupt the ECC memory to test the ECC check ?

5. TRM mentions about the RAM ECC even Register (0xFFFF_F800) and odd register (0xFFFF_F900). What are these ? Do i need to enable/disable registers in both locations as a part of step 2 of section 3.4 of ECC application note ?

6. How to enable the ECC error interrupt ?

7. How to introduce the single and double bit error ? And how to verify that error is occured ?

over 12 years ago

0 Enrique Lizarraga over 12 years ago

TI__Expert 4580 points

Hello:

This is just a confirmation that we received your post and will work on that. Most of our experts are out of the office this week, your answer could be delayed.

Regards,

Enrique Lizarraga

0 Bindu Tanguturi over 12 years ago in reply to Enrique Lizarraga

Expert 1180 points

Any update please.

0 Bindu Tanguturi over 12 years ago in reply to Bindu Tanguturi

Expert 1180 points

Any update please.

0 Sunil Oak over 12 years ago

TI__Mastermind 49120 points

Hi Bindu,

Please excuse us for taking this long to answer this post. I will try to answer each question below.

Development Environment : Processor : TMS570LS20216 (Cortex R4), Code Composer Studio : 4.2.0.10018, TMS470 C/C++ CODE GENERATION TOOLS 4.6.3

1. In some posts, it was mentioned that SPNA126.pdf need some updations in documentation. Where can i get the latest version of SPNA126.pdf ?

>> Yes, this app note needs some updates. I will have to check on the expected date for when the update will be available.

>> The memory initialization routine defined in the sys_memory.asm file uses a constant called ramInitMask. The value of this constant is used to set the appropriate bits in the system module MSINENA register. The datasheet has a table that shows the bit numbers associated with each memory on the device. This is table 2-7 on page 15 of SPNS141F.

3. The sample code available for the RAM ECC testing is for the CCS version 3. Is there any sample code available for the above development enviroment mentioned ?

>> The sample code as such will work as-is even with the new development environment. You may need to create a new project and then add the individual source files manually. We will also look to update the code example for the new development environments when we update the app note.

>> You are correct: the sequence described in section 3.4 of the app note is not correct and needs to be rewritten.

The Cortex-R4F CPU always writes both the data and the corresponding ECC value for every write to the CPU RAM (also called tightly-coupled RAM, TCRAM). So it is not possible to test RAM ECC error generation by corrupting data in actual RAM. The TCRAM interface module includes a bit that allows the CPU to also directly write to the RAM ECC locations. This is the ECC WR EN bit in the RAM CTRL register. Note that there are two TCRAM interface modules for the two tightly-coupled RAM interfaces of the CPU. It is just easier to enable the ECC writes in both the interface modules.

Please follow the sequence as follows:

#define tcram1bitError 	(*(unsigned int *)(0x08400000))
#define tcram2bitError 	(*(unsigned int *)(0x08400008))

#define tcram1bit		(*(unsigned int *)0x08000000)
#define tcram2bit		(*(unsigned int *)0x08000008)

void checkRAMECC(void)
{
	volatile unsigned int ramread = 0;

	tcram1REG->RAMCTRL = 0x0005010A;			// enable writes to ECC RAM, enable ECC error response
	tcram2REG->RAMCTRL = 0x0005010A;

	tcram1REG->RAMTHRESHOLD = 0x1;				// the first 1-bit error will cause an error response
	tcram2REG->RAMTHRESHOLD = 0x1;

	tcram1REG->RAMINTCTRL = 0x1;				// allow SERR to be reported to ESM
	tcram2REG->RAMINTCTRL = 0x1;

	tcram1bitError ^= 0x1;						// cause a 1-bit ECC error
	tcram1REG->RAMCTRL = 0x0005000A;			// disable writes to ECC RAM
	tcram2REG->RAMCTRL = 0x0005000A;

	ramread = tcram1bit;						// read from location with 1-bit ECC error
	if (!((tcram1REG->RAMERRSTATUS & 1) || (tcram2REG->RAMERRSTATUS & 1)))	// SERR not set in TCRAM1 or TCRAM2 modules
	{
		tcramClass2Error();						// TCRAM module does not reflect 1-bit error reported by CPU
	}
	else
	{
		tcram1REG->RAMERRSTATUS = 0x1;			// clear SERR flag
		tcram2REG->RAMERRSTATUS = 0x1;
		esmREG->ESTATUS1[0] = 0x14000000;		// clear status flags for ESM group1 channels 26 and 28
	}

	tcram1REG->RAMCTRL = 0x0005010A;			// enable writes to ECC RAM, enable ECC error response
	tcram2REG->RAMCTRL = 0x0005010A;

	tcram2bitError ^= 0x3;						// cause a 2-bit ECC error
	ramread = tcram1REG->RAMCTRL;
	ramread = tcram2REG->RAMCTRL;

	ramread = tcram2bit;						// read from location with 2-bit ECC error
												// this will cause a data abort to be generated
}

You can call the above function once the CPU RAM has gone through the auto-initialization process (both RAM and ECC are initialized). Note that the last read in the above code sequence will cause a data abort exception. The data abort handler must look for whether the abort has been intentionally caused by inducing a double-bit error in the TCRAM. If so, then you can switch the processor back to the mode in which it was when the abort occurred, and return back to the instruction after the one that was aborted.

>> The CPU has two separate tightly-coupled interface ports for the data RAM. These are referred to as B0TCM and B1TCM in ARM's literature for the Cortex-R4F processor. Each of these two ports interface to its own module that manages the accesses to the RAM module connected to the port. Therefore there are two TCRAM interface modules to be configured. Their base addresses are 0xFFFFF800 and FFFFF900.

6. How to enable the ECC error interrupt ?

>> Each error signal on the device is connected to the Error Signaling Module (ESM) as one of the error inputs. For example, a single-bit TCRAM error is indicated to the ESM's group1 channels 26 or 28 (depending on whether the error occurred due to an access to B0TCM or B1TCM). The ESM allows the application to choose the response to each error input to group1 errors. There are two responses: interrupt CPU and/or toggle external nERROR pin. Both these actions are configurable for group1 errors, and are configured via the ESM registers ESMIEPSR1 (for nERROR action) and ESMIESR1 (for interrupt to CPU).

7. How to introduce the single and double bit error ? And how to verify that error is occured ?

>> Please refer to the above checkRAMECC function. It shows you how to introduce and check for single-bit and double-bit errors. You still have to write your own data abort handler to handle a deliberately caused double-bit TCRAM error. This same data abort handler will also be used when you are testing double-bit errors from the flash (connected to ATCM port of CPU).

Regards, Sunil

0 Bindu Tanguturi over 12 years ago in reply to Sunil Oak

Expert 1180 points

Thanks for the detailed explanation Sunil. I will work on this for next two days and get back to you if i see any problem.

Thanks again.

0 Bindu Tanguturi over 12 years ago in reply to Bindu Tanguturi

Expert 1180 points

Hi Sunil,

I have gone through the first few responses and i am working on the remaining responses.

As per your response below is my understanding and few clarifications required for first few responses.

a) I have understood that _memoryIni_t function does the RAM Memory Initialization Using hardware as mentioned in the section 3.1.2 of SPNA126. Is that correct ?

b) Below is the _memoryInit_ function that is available in the code generated from HALCOgen.I do not see the ramInitMask constant in the below code. Can you confirm me on my understanding of below code.

My understaning is that MINITGCR is loaded with 0x0A which indicates that 'automatic hardware memory initalization' is enabled.And then MSIENA register is loaded with 0x657F. This value should be the ramInitMask that you are referring.This register is used to enable the memory modules which need to be intialized during automatic hardware memory intialization. Get the value of register (MSTCGSTAT). Verify that Memory intialization is complete. If not wait for the completion.

Once intialization is done, then disable the automemory intialization.

One question here: the code should be "beq mloop" or "bneq mloop" ?

;-------------------------------------------------------------------------------

; Initialize memory

.global _memoryInit_

.asmfunc

_memoryInit_:

ldr v9, regMinitGcr ; MINITGCR register pointer

mov v1, #0xA

str v1, [v9]

mov v1, #0x657F

str v1, [v9, #4]

mloop:

ldr v2, [v9, #12]

tst v2, #0x100

beq mloop

mov v1, #5

str v1, [v9]

bx lr

regMinitGcr: .word 0xFFFFFF5C

.endasmfunc

;-------------------------------------------------------------------------------

c) I have enabled the ECC RAM check before the RAM intialization. Is that correct ? Because the ECC RAM intialization is mentioned after the memory inti as per the step 2 of section 3.4 of SPNA126.

d) Why the bits 15 to 31 are not mapped in the table 2-7 of SPNS141F (TMS570 data sheet) ?

0 Bindu Tanguturi over 12 years ago in reply to Bindu Tanguturi

Expert 1180 points

Hi Sunil,

I have gone through the first few responses and i am working on the remaining responses.

As per your response below is my understanding and few clarifications required for first few responses.

a) I have understood that _memoryIni_t function does the RAM Memory Initialization Using hardware as mentioned in the section 3.1.2 of SPNA126. Is that correct ?

Once intialization is done, then disable the automemory intialization.

One question here: the code should be "beq mloop" or "bneq mloop" ?

;-------------------------------------------------------------------------------

; Initialize memory

.global _memoryInit_

.asmfunc

_memoryInit_:

ldr v9, regMinitGcr ; MINITGCR register pointer

mov v1, #0xA

str v1, [v9]

mov v1, #0x657F

str v1, [v9, #4]

mloop:

ldr v2, [v9, #12]

tst v2, #0x100

beq mloop

mov v1, #5

str v1, [v9]

bx lr

regMinitGcr: .word 0xFFFFFF5C

.endasmfunc

;-------------------------------------------------------------------------------

c) I have enabled the ECC RAM check before the RAM intialization. Is that correct ? Because the ECC RAM intialization is mentioned after the memory inti as per the step 2 of section 3.4 of SPNA126.

d) Why the bits 15 to 31 are not mapped in the table 2-7 of SPNS141F (TMS570 data sheet) ?

0 Sunil Oak over 12 years ago in reply to Bindu Tanguturi

TI__Mastermind 49120 points

Hi Bindu,

See my comments below in blue.

a) I have understood that _memoryIni_t function does the RAM Memory Initialization Using hardware as mentioned in the section 3.1.2 of SPNA126. Is that correct ?

>> Yes, the memoryInit function uses the hardware for initializing the selected memories.

Once intialization is done, then disable the automemory intialization.

One question here: the code should be "beq mloop" or "bneq mloop" ?

>> The "tst v2, #0x100" instruction basically runs a bit-wise "AND" operation on the contents of v2 and 0x100. So you are correct: the "beq" must be replaced with "bne".

c) I have enabled the ECC RAM check before the RAM intialization. Is that correct ? Because the ECC RAM intialization is mentioned after the memory inti as per the step 2 of section 3.4 of SPNA126.

>> The RAM ECC check must be enabled once the RAM has been initialized. You could see ECC errors if you reverse the order. Any write to the CPU RAM that is not a 64-bit value causes the CPU to perform a read-modify-write operation. If the CPU detects an ECC error during the read phase, it will cause an abort exception.

d) Why the bits 15 to 31 are not mapped in the table 2-7 of SPNS141F (TMS570 data sheet) ?

>> The lower 16 bits are sufficient to be able to select each on-chip SRAM on the microcontroller. The remaining bits in the MSINENA are reserved.

0 Sunil Oak over 12 years ago in reply to Sunil Oak

TI__Mastermind 49120 points

Hi Bindu,

I made a mistake yesterday:

>> The "tst v2, #0x100" instruction basically runs a bit-wise "AND" operation on the contents of v2 and 0x100. So you are correct: the "beq" must be replaced with "bne".

The TST instruction ANDs the contents of the MSTCGSTAT register with 0x100. We are looking for the bit 8 to get set. In that case, the TST instruction will result in a zero until the bit 8 gets set. So the original "BEQ" is correct.

Regards, Sunil

Arm-based microcontrollers

Arm-based microcontrollers forum

RAM ECC Testing