Comparing clocks in different RM4 uC

Francisco,

You will have to use the EXTCLKIN1 and EXTCLKIN2 of counter 1 on the DCC1 module for this task. All other inputs to DCC1/2 modules are internal signals. You can use the following code example for generate the ECLK with difference sources and setting up DCC1 with OSCIN as reference on counter 0 to make the period on input to counter 1.

void ECLK_Config(unsigned int mode, unsigned int clk_source) // mode =0 normal, 1 test; clk_source =0 oscin, 1 pll
{
    register SYSTEM_ST *ptr  = (SYSTEM_ST *)SYSTEM;
    ptr->SYSPC1_UN.SYSPC1_UL = 1;  // Functional ECLK pin
    ptr->ECPCNTLR_UN.ECPCNTLR_ST.ECPCOS_B1 = 1; // Eclk Continue on Suspend

    if (mode == 0)  //normal ECLK mode
    {
        ptr->ECPCNTLR_UN.ECPCNTLR_ST.ECPDIV_UB = 1;   //ECLK = VCLK/2
        if (clk_source == 0)
            ptr->ECPCNTLR_UN.ECPCNTLR_ST.ECPSSEL_B1 = 0; //0 for VCLK
        else
            ptr->ECPCNTLR_UN.ECPCNTLR_ST.ECPSSEL_B1 = 1; //1 for OSCIN
    }
    else  //Clock Test Mode
    {
        ptr->CLKTEST_UN.CLKTEST_ST.CLK_TEST_EN_B4 = 5;
        ptr->CLKTEST_UN.CLKTEST_ST.SEL_ECP_PIN_B4 = clk_source;
    }
}

unsigned int DCC_Cycles(unsigned int CLK_Source,unsigned int Test_Time)
{
    register unsigned int Cycles;
    register DCC_ST    *DCC_Ptr = (DCC_ST *) DCC1;

        /* Set up the DCC module */

        /* Clear any flags set in the DCCSTAT register */
        DCC_Ptr->DCCSTAT_UN.DCCSTAT_UL = 0x3;

        /* Counter 0 will be loaded with test time (count) */
        DCC_Ptr->DCCCNTSEED0_UN.DCCCNTSEED0_UL = Test_Time - 4;
        DCC_Ptr->DCCVALIDSEED0_UN.DCCVALIDSEED0_UL = 4;

        /* Set up Counter 1 for max time */
        DCC_Ptr->DCCCNTSEED1_UN.DCCCNTSEED1_UL = 0x000fffff;
        
        /* Enable selected clock as source for counter 1 */
        DCC_Ptr->DCCCLKSRC1_UN.DCCCLKSSRC1_UL = 0xA000|CLK_Source;

        
        /* Start count, enable single shot, done and error flags */
        DCC_Ptr->DCCGCTRL_UN.DCCGCTRL_UL = 0xAAAA;

        /* Wait until the DCC Done and/or ERROR flag is set */
        while (!(DCC_Ptr->DCCSTAT_UN.DCCSTAT_UL & 0x3));

        Cycles = 0xfffff -  DCC_Ptr->DCCCNT1_UN.DCCCNT1_UL;

        return Cycles;
}

Thanks and regards,

Zhaohong

When applying Zhaohong's advice, please remember to utilize a clock divider on the ECLK output signal which allows the internal frequency to be adapted suitable for input on the EXTCLKIN pins.  Reducing the frequency will also help mitigate potential EMI issues of driving a high speed clock between the devices.

Regards,

Karl