What's up with PE3?

Hello back,

Agree - wonder if late night, surely needed rebrand, "cut/paste" manual creation ran bit amuck - re: PE3. 

Can report that our older LX4F (64 pin QFP) also has such pin - and both it and neighbor PE2 - are uniquely "barren" - upon otherwise well-fruited plain...  (i.e. PE2,3 may serve as AIN or GPIO - but zero alternate functions listed - while all others (beyond Power, Reset, Xtal etc.) overflow w/alternate/selectable functionality...)

Should vendor not be, "quick draw" - would not quick/easy experimentation - across several devices - reveal/comfort.

btw: glossy wooden plank (starboard side - your "land-locked" honor) gleams forlornly - in your absence...

Hello CB1,

I have spotted a bit more information:  On the previous datasheet page, a forward-reference to the table in question reads "Some GPIOs when configured as inputs require a strong pull-up resistor to maintain a threshold above VIH during power-on. See Table 23-28 on page 1338".  So, it appears that the pin should function normally in output mode - my intended use.  Not sure about the necessity of the qualifying "...during power-on"(?)  I would still appreciate some definitive insight from TI though...

I will not disagree with your logic in suggesting I just test it.  In fact I have a couple of LM4F232 Evaluation Boards (very nice board BTW).  I will confess though that when I'm in the design phase I like to stick to the data sheet as much as possible.  If I don't understand a seemingly random tidbit in the datasheet, I can get only limited satisfaction from testing - there's always the nagging doubt hanging over my shoulder that there's more to the story...  My wife thinks I'm paranoid - but she's not a engineer!

The arrival of 64-pin TM4C123FH6PMI at a few distributors has pulled me back from the brink, as I was about to "jump ship" to a competing (although much faster) part.  Changing over may be necessary in the future, but that depends on TI's (invisible) roadmap.  Might you be one and the same as handle "jj.sprague" on  forum of much faster part?

As always, thank you for your kind support!

Best Regards,

Dave

Bonjour Dave,

Bingo - crack cover penetrated...  (and your use of "much faster" (168MHz) shows care/compassion beyond other here...) (for extra credit - care to ID ST7 - too?   not this reporter...)

Your wife not alone - her assessment.

Note that errata often assumes, "living/breathing" status - even "sworn deposition" from vendor staff today - may "switch" downstream...  (only thing sure - expect and be prepared to accept change!)

Any new issue always brings uncertainty - and there's a significant process change (65 nm - iirc) in this mix.  Trained beyond engineering - your hoped for, "definitive insight" may not arrive in that full, binding form.  Hard evidence - quickly/easily achieved (by you/me) this case - requires process change to impact/alter - thus my preference. 

Insight/spec surely will better cement/comfort w/time - many pioneer bodies - loitering early, mal-formed trail...  (and those bodies "ramping" - none of those mine - yet!)   

Recall past adage - "Trust but Verify" - may hold this case as well...  You are most welcome - I've gleaned much - your participation too...  And - may that roadmap be woven from same cloth as famed, Emperor's finery?   

Dave,

Just issued a "cb-source 2 conversation" further outlining my beliefs - this issue...

I would still appreciate some definitive insight from TI though...  BUMP!  TI please respond!

Hi Sue,

My apologies for neglecting to respond to this post!!!  Indeed, you answered my question and I appreciate it.  I'm using PE3 as AIN0 and it is functioning fine.  Thanks again!

Regards,

Dave

No worries, Dave!  I just like to check things off when they are complete!  It helps me keep track of my open items.  I'm glad that I was able to address your concerns.

Regards,

Sue

Hi Sue,

Is it ok to use external pull down instead of pull up on PE3? The pin is configured as an input and the processor is TM4C1230C3PMI.

Thanks,

Sanja

Sue's not been seen in quite awhile - this fruited plain.

Targeting Amit may prove a more productive strategy.

it's normal to have your input "active low" thus pull-up dominates as "normal" input treatment.  Pulling down requires that your active signal drive high - with sufficient current to reach the input Vih threshold of PE3.

Active "low" is preferred as you avoid routing 3V3 (or beyond) off your board to serve as input signaling source.  (Ground only is all that's required when pull-up Rs are employed - that's the historical justification - should you care...)

What you said makes sense. I would still like to get an official confirmation from TI. What is the best way to get the response from TI?

Thanks,

Sanja

Sue was pretty direct in her response - although her justification remains unstated.

As this post is ticked as "verified" it does not receive the full attention of forum staff.  Perhaps a new post - asking specifically, "May PE3 employ a pull-down rather than the recommended pull-up - when used as an input?"

For completeness I'd link to this post - so that Sue's (past) response is quickly/easily available.

A simple voltage comparator (such as LM339) accomplishes Sue's directive for pull-up (the comparator's open collector output - needs such) and may be implemented so that either a logic high or low (@ 339 input) will be "felt" @ MCU's PE3.

Also since Sue noted that these pins were used in testing it could well be that pulling these low will place the chip in some sort of factory test mode.

Robert

Great point Robert - especially if PE3 is low upon power up.  (I'd bet that's how that test mode is entered...)

With the ready availability of JTAG/SWD - use of PE3 (for testing) seems unusual/non-standard - while the limited PE3 documentation provides little comfort/guidance.  (sole appearing detail/guidance found (naturally) just here!)

Let the (PE3 usage violating) user beware...

Hello All,

PE3 does not have an issue. It is commonly used for ADC. The test mode will not have a conflict.

Regards

Amit

Hi Amit,

So the external pull down is ok? If I understand correctly, it's only when the pull up is used that it needs to be between 1k and 10k?

Regards,

Sanja

Hello SoCalHrdwr

I have used a Pull down once on PE3 for some testing, and have not seen an issue. Might be a good idea to have a Pull Down connected to PE3 on a launchpad and see if it works as a GPIO.

Regards

Amit