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SECDED in TMS570

David Sabol
Genius 4850 points

I have a question about SECDED in the TMS570.  I'm sure the answer is simple, but I haven't been able to find it.

 

My understanding is that ECC is separate for RAM and FLASH.  I can see how to enable both of these, and see how to enable an interrupt to be generated if a single error is detected.  However, I can't what this interrupt maps. I can also see in the status register where you can see if a double error has been detected, but I can't see where an interrupt can be enabled or where it maps to.  For double errors, are there interrupts?

 

Thanks,

David

  • 0
    TI__Guru 68810 points

    David,

    You won't find ECC in the interrupt table.  However ECC errors can go to ESM and ESM shows up in the interrupt table.  High priority ESM errors go to channel 0 which is an NMI (FIQ) interrupt.  The other ESM errors go to the low level which can be programmed as IRQ or FIQ (although the norm woudl be IRQ).

    ECC errors also generate a CPU abort, not an interrupt (directly).  You can find this described in the ARM Cortex-R4 TRM.  We don't publish this but you can get it from ARM's website (see 'support').  You want the "Level One Memory System" chapter and you want to read through "Fault Handling'.