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TMS570LC4357: L2RAMW and SECDED Testing

Christopher TRITANT
Expert 1080 points
Part Number: TMS570LC4357

Hello,

We are using the TMS570LC4357 and we need more information about the L2RAMW  ?

The reference manual does not describe clearly how to perform testing of RAM SECDED.

For example: "Write test vectors DIAG_DATA_VECTOR_H, DIAG_DATA_VECTOR_L, DIAG_ECC, and RAMADDRDEC_VECT with desire test irritants"
But in this case, what means desire test irritants ?

Could you explain us this sentence and more generally how to perform a testing for RAM and RAM SECDED?

Best regards,

Christopher

  • 0
    TI__Guru**** 192486 points

    Hello Christopher,

    1. DIAG_DATA_VECTOR_H, DIAG_DATA_VECTOR_L is the value of one location in SRAM

    2. DIAG_ECC is its ECC value at ECC memory range (starting from 0x08400000).

    3. at test mode, inverting 1 bit or 2 bit of the ECC value in DIAG_ECC will cause 1-bit or 2-bit ECC error

    • #define L2RAM_SYN_1BIT_DATA_ECC ((uint64)0xCECECECECECECECEU)/*this corrupts the ecc for data bit 0*/
    • #define L2RAM_SYN_2BIT_DATA_ECC ((uint64)0x0303030303030303U)/* this corrupts the ecc for 2 bit error*/
    • volatile uint64 sramEccTestBuff[2] = {0x0u};
    • volatile uint64* eccB1;
    • volatile uint32* buffPtr;
    • sramEccTestBuff[2] = 0UL;
    • eccB1 = &sramEccTestBuff[0];
    • /* Write test vectors */
    • l2ramwREG->DIAGDATAVECTOR_H = *buffPtr;
    • buffPtr++;

    • l2ramwREG->DIAGDATAVECTOR_L = *buffPtr;
    • l2ramwREG->DIAG_ECC = (*eccB1) ^ L2RAM_SYN_2BIT_DATA_ECC;
    • l2ramwREG->RAMTEST = (uint32) 0x0000008Au; /* 1->Trigger, 8->Eq., test mode, A->Test enable */
    • l2ramwREG->RAMTEST |= (1 << 8);

    Please refer to the safety diagnostic library for details.