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RM48 EMIF NAND Flash addressing

Other Parts Discussed in Thread: HALCOGEN

Hi,

I am trying to use TH58BVG3S0HTAI0 (toshiba.semicon-storage.com/.../lookup.jsp;region=ncsa&lang=en_us?). This NAND uses same IO pins for addressing, data, and commands. I was reading the RM48 reference document, and I can't figure out how to communicate with the chip using EMIF. EMIF looks like it is expecting separate data and addressing pins.

Thank you.

  • Hi Alex,

    You would need to write a driver for the NAND. It will be a block device, i.e. you can't directly access it and execute in place from it. You'll need to load a block, process the ECC, all in software.

    Also please be aware of Errata EMIF#4 www.ti.com/.../spnz223.pdf
    The extra chip select pulses you'll want to avoid because the NAND will respond to them, so you need to make sure you have the MPU memory type setup correctly as the errata explains.
  • Anthony,

    I was thinking that I would have to be talking to the NAND by wrtiting to the pins directly. By your response, can I do the data transfer portion using EMIF (EMIF takes care of the data and RE/WE? Do I just write to EMIF memory location (for example, EMIF CS2 0x6000_0000) a block and then I wait for the busy pin to clear?

    Thanks for the help!

    Alex

  • Hi Alex,Yes, basically. I wasn't able to pull down the spec the other day.
    But generally it'll be one or two addresses that you'll read and write from, and to send the NAND a command followed by data you'll just write the command and data to the flash. Or you might write a command followed by reads of data.
    The 570 has a WAIT input and you could use this to hold off the access during a 'busy' but I would probably not recommend this unless you use it with DMA. Otherwise the CPU will slow down a lot.
    Best Regards,Anthony

     

    EDIT:  I should clarify - it's probably just one address you'd read and write to / from as you suggest in your last post.

    But if the NAND chip has some other 'mode' pin - then sometimes you might hook it up to an address line,  so that reading from base + 0x00000 would make the mode pin go one way and base + 0x0001xx would make the mode pin go the other way.   The addresses are bogus in the last example - you would need to look at your design to get the right address bit to flip as it will depend on which address line you connect to the NAND.   But I'm not even sure your NAND has anything special like this so start out thinking just the way you were...  it's probably correct.

  • I have ASIZE as 8bit in Halcogen. When I try writing to the EMIF location:

    *(uint8 *)(0x60000000) = (uint8)0x90;

    I was expecting to get 1 pulse, but I get 3 pulses on WE. I have the MPU setup in that EMIF address range as strongly ordered per errata. 

    Any ideas?

    Thank you!

  • Hi Alex,Could you please step through this line in the form of assembly code?
    There should be a single "STRB" instruction and if you step over that you should see 1 WE\ if everything is working correctly.
  • I stepped through the assembly. I can see it calling STRB, but stepping through that, it gives me 3 pulses on WE.

  • Hi Alex,
    This doesn't make sense if the MPU is actually configured for strongly ordered. Would it be possible for you to upload your project?
    Alternatively we could start with your MPU settings. Need to check how they are configured - as there is a priority involved and it's possible that you may have a higher MPU channel overriding the one you set up with the strongly ordered properly. And we need to make sure your MPU settings are being programmmed and that the MPU is enabled.
  • It was the MPU. I had it set up in Halcogen, but didn't call the init function.

  • Great Alex!  Glad you were able to resolve this issue.