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I am configuring the RM48L952ZWT boot loader for ADC use per specification.
Sadly, HAL Code Generator does not give registers, so hence some questions.
1. Is ADC1 Group 1 (see picture above) the Group 1 specified at 0xFF7C07C? I will assume that ADC1 Group Event is really "ADC1 Group 0".
Write the bits corresponding to the channels to be converted in group 1 by writing 0x00FFFFFF to the Group 1 Channel Select Register (ADG1SEL at 0xFFF7C07C). This will start the conversions. Wait 10 msec. before reading the conversion data. All channels will be continuously converted, with a period of approximately 9.8 msec.
2. Am I correct that the way to enable the ADC state machine is to check the "Enable ADC drivers | ADC1" check box on the RM48L952ZWT Driver Enable tab, such as I did in the screenshot below?
Write 0x81140001 to the ADC EN bit of the Operating Mode Control Register (ADOPMODECR at 0xFFF7C004) to enable the ADC state machine.
3. My requirement is to set the ADCLK frequency to VCLK/32 from the default VCLK/2. Does that mean that I would increase the "Cycle time (ns)" field from the default 100 to 100 * 16 or 1600?
Configure the ADCLK frequency to VCLK/32 by writing 0x0000001F to the clock divider into the Clock Control Register (ADCLOCKCR at 0xFFF7C008). Note that VCLK was previously set to the oscillator frequency (20MHz) divide by 2, or 10Mhz.
4. I do not see any memory mapping, so am I correct that the default behavior is as shown in the following requirement, meaning that I do nothing here?
Set the pointers to the ADC conversion results memory by writing 0x0010001C to the ADC Results Memory Configuration Register (ADBNDCR at 0xFFF7C058). (Section 19.11.23) This sets the Ch0 results to be the 32-bit word at 0xFF3E0020, the Ch1 results to be the 32-bit word at 0xFF3E0024, and so on until the Ch23 results to be the 32-bit word at 0xFF3E0034.
5. Does ADC1 automatically get released from reset by enabling ADC1 on the driver enable page?
Write 0x00000000 to the ADC Reset Control Register (ADRSTCR at 0xFFF7C000) to release the ADC module from the reset state. (Section 19.3.11)
HI Sarah,
1. Yes, ADC1 Group1 corresponds to ADC Group1 Channel select register at 0x7C offset. If you go to the TRM, we use ADC Group1, Group2 and Event Group. We don't start with Group0.
2. Enable the ADC driver will only make the HalCoGen generate the drivers/APIs code for ADC module. It does not enable the state machine. Any module which is unchecked you will not see their C files generated.
3. yes.
4. Please refer to the ADBNDCR register in the TRM and also see below. You can divide the available ADC buffers among the three different groups.
5. No, by enabling the driver will only generate the MiBADC module drivers/API code which is contained in the file called adc.c You need to release the MibADC module from reset by writing a '0' to theADRSTCR register. This needs to be done by the application.
Yes, each word is a 32-bit. Please go to section 'Reading Conversion Results Directly from the Conversion Results' Memory' for details. I'm showing a snippet below. Each conversion result occupies a 32-bit logical word space.
Memory Configuration Register
I have the requirement, as mentioned earlier, to initialize the Memory Configuration Register, which sets memory boundaries and word length.
Set the pointers to the ADC conversion results memory by writing 0x0010001C to the ADC Results Memory Configuration Register (ADBNDCR at 0xFFF7C058). (Section 19.11.23) This sets the Ch0 results to be the 32-bit word at 0xFF3E0020, the Ch1 results to be the 32-bit word at 0xFF3E0024, and so on until the Ch23 results to be the 32-bit word at 0xFF3E0034.
You mentioned in your reply that the conversion results are at the locations specified above. What was not said is where the initialization gets done and if I have to do something toward that aside from calling adcInit(), which I am already doing.
I looked at the adcInit() function and the closest location that appears relevant, though I do not see a Memory Control Register, is the highlighted code shown here.
Do I need to do something?
Where is the required initialization done?
Hi Sarah,
In order to match your EE's comment where it says to write 0x0010001C to the BNDCR register you will need to configure the HalCoGen ADC1 Memory like below. This will reserve 8 buffers for Event group and 24 buffers for Group1. This is why he says about the 24 channels with ch0 mapped to 0xFF3E0020.
Hi Sarah,
1. Actually your EE's comment is not really correct. Perhaps you want to check with him/her again.The comment in 'Set the pointers to the ADC conversion results memory by writing 0x0010001C to the ADC Results Memory Configuration Register (ADBNDCR at 0xFFF7C058). (Section 19.11.23) This sets the Ch0 results to be the 32-bit word at 0xFF3E0020, the Ch1 results to be the 32-bit word at 0xFF3E0024, and so on until the Ch23 results to be the 32-bit word at 0xFF3E0034'. is contradictory. These two highlighted are contradictory to each other. Let me explain.
I deduced from your EE's comment. He said "by writing 0x0010001C to the ADC Results Memory Configuration Register (ADBNDCR at 0xFFF7C058)."
If you go to the Userguide, see below snippet, the bits from 24:16 is the BNDA and the bits 8:0 is the BNDB. With the 0x0010001C commented by your EE, it means the BNDA is 0x10=16 (decimal) and BNDB is 0x1C=28 (decimal). This means that he has reserved 2*16=32 buffers for the Event Group. The number of buffers for Group 1 is 2 * (BNDB - BNDA) = 2 * (28 - 16) = 24. However, he later said that Ch0 will start at 0xFF3E020. This implies that the Event Group buffers will occupy from address 0xFF3E000 to 0xFF3E020. This address range only gives 8 32-bit buffers. This is why I said his statements are contradictory. My guess is that he thinks the buffers are only 8-bit wide. If the buffers are only 8-bit wide then 0xFF3E000 to 0xFF3E020 would have given you 32 8-bit buffers. So I don't really know how many buffers he wants for the Event Group. is it 8 32-bit buffers or 32 32-bit buffers. You really need to check with your EE. I would not know your EE's original application intention. If your EE's comment is really meant to have 32 32-bit buffers for the Event Group then the Ch0 for the Group1 would have to start at 0xFF3E0080 instead, not 0xFF3E0020.
Please also go to the ADC userguide. How the buffers are partitioned is described. there.
If your EE really wants 32 buffers for event group and 24 buffers for Group1 then below is the HalCoGen setting and this will give you 0x0010001C written to the register.
2. See above explanation on how BNDA and BNDA are used in calculation.
3. No, you can partition whatever number of buffers for each group. For example, you can configure 6 buffers for Event Group and 14 buffers for Group1 and the remaining (64-6-14)=44 will be reserved for Group2. BNDA in this case will be 3 and BNDB will be 10. 2*3=6 gives you 6 buffers for Event Group. 2*(10-3)=14 buffers for Group1.
4. See explanation in #1. BNDA is a pointer to the end of Event group or the beginning of Group1. The first buffer in event group will start at 0xFF3E0000. The starting address of Group1 buffers will depend on what BNDA is. You just shift left by two bits of the value of 2*BNDA to get the starting address of Group1.
