Hercules RM48L952ZWT: HAL Code Generator (ADC)

HI Sarah,

  1. Yes, ADC1 Group1 corresponds to ADC Group1 Channel select register at 0x7C offset. If you go to the TRM, we use ADC Group1, Group2 and Event Group. We don't start with Group0. 

  2. Enable the ADC driver will only make the HalCoGen generate the drivers/APIs code for ADC module. It does not enable the state machine. Any module which is unchecked you will not see their C files generated. 

  3. yes.

  4. Please refer to the ADBNDCR register in the TRM and also see below. You can divide the available ADC buffers among the three different groups.

  5. No, by enabling the driver will only generate the MiBADC module drivers/API code which is contained in the file called adc.c You need to release the MibADC module from reset by writing a '0' to theADRSTCR register. This needs to be done by the application.

  

#2 (ADC State Machine): You said no, but did not offer the how a developer should enable the ADC state machine? Is that a custom code by writing to a register once the HAL Code Generator generates the source code or is there a way to do that in HalCodeGen?

#4 (Memory Mapping) How many bits is one "word" here?

Does each word above mean 32-bits? More specifically, 2 * BNDA(8) = 16 words = 16 words = 16 32-bit words?

You will need to release the ADC from reset. Normally in your application you will need to call adcInit(). adcInit() is an API that will initialize all the registers per your HalCoGen configuration. The very first thing the adcInit() will do is to release the ADC module from reset. Once the MibADC module is initialize you can start the conversion by writing the channels that you want to convert in the channel select registers. HalCoGen provides an API called adcStartConversion() to start the conversion. I will suggest that in HalCoGen you go to Help->Help Topics->Modules->ADC for a list of available API. You can also go to Help->Help Topics->Examples to see various examples on using various different modules on the device.

Thank you for the info, as I did not know about needing to call adcInit() and the API, which is must know information.

That does not answer the state machine or word questions that I asked above.

Yes, each word is a 32-bit. Please go to section 'Reading Conversion Results Directly from the Conversion Results' Memory' for details. I'm showing a snippet below. Each conversion result occupies a 32-bit logical word space. 

Memory Configuration Register

I have the requirement, as mentioned earlier, to initialize the Memory Configuration Register, which sets memory boundaries and word length.

Set the pointers to the ADC conversion results memory by writing 0x0010001C to the ADC Results Memory Configuration Register (ADBNDCR at 0xFFF7C058). (Section 19.11.23) This sets the Ch0 results to be the 32-bit word at 0xFF3E0020, the Ch1 results to be the 32-bit word at 0xFF3E0024, and so on until the Ch23 results to be the 32-bit word at 0xFF3E0034.

You mentioned in your reply that the conversion results are at the locations specified above. What was not said is where the initialization gets done and if I have to do something toward that aside from calling adcInit(), which I am already doing.

I looked at the adcInit() function and the closest location that appears relevant, though I do not see a Memory Control Register, is the highlighted code shown here.

Do I need to do something?

Where is the required initialization done?

Hi Sarah,

 In order to match your EE's comment where it says to write 0x0010001C to the BNDCR register you will need to configure the HalCoGen ADC1 Memory like below. This will reserve 8 buffers for Event group and 24 buffers for Group1. This is why he says about the 24 channels with ch0 mapped to 0xFF3E0020.

Hi Charles,

I complied, thank you, however I want to understand so that the next time that I have to do something that I can make the configuration on my own.

1. How did you know to make the length 24 on BNDB and not BNDA?

2. Why is the length of BNDA 8 and not some other number?

3. Does the total (BNDA + BNDB) always need to equal 32 words regardless of project?

4. Does the address of BNDB map to 0xFF3E0020? If so, then what does BNDA map to?

Hi Sarah,

 1. Actually your EE's comment is not really correct. Perhaps you want to check with him/her again.The comment in 'Set the pointers to the ADC conversion results memory by writing 0x0010001C to the ADC Results Memory Configuration Register (ADBNDCR at 0xFFF7C058). (Section 19.11.23) This sets the Ch0 results to be the 32-bit word at 0xFF3E0020, the Ch1 results to be the 32-bit word at 0xFF3E0024, and so on until the Ch23 results to be the 32-bit word at 0xFF3E0034'. is contradictory.  These two highlighted are contradictory to each other. Let me explain. 

 I deduced from your EE's comment. He said "by writing 0x0010001C to the ADC Results Memory Configuration Register (ADBNDCR at 0xFFF7C058)."

 If you go to the Userguide, see below snippet, the bits from 24:16 is the BNDA and the bits 8:0 is the BNDB. With the 0x0010001C commented by your EE, it means the BNDA is 0x10=16 (decimal) and BNDB is 0x1C=28 (decimal).  This means that he has reserved 2*16=32 buffers for the Event Group. The number of buffers for Group 1 is 2 * (BNDB - BNDA) = 2 * (28 - 16) = 24. However, he later said that Ch0 will start at 0xFF3E020. This implies that the Event Group buffers will occupy from address 0xFF3E000 to 0xFF3E020. This address range only gives 8 32-bit buffers. This is why I said his statements are contradictory. My guess is that he thinks the buffers are only 8-bit wide. If the buffers are only 8-bit wide then 0xFF3E000 to 0xFF3E020 would have given you 32 8-bit buffers. So I don't really know how many buffers he wants for the Event Group. is it 8 32-bit buffers or 32 32-bit buffers. You really need to check with your EE. I would not know  your EE's original application intention. If your EE's comment is really meant to have 32 32-bit buffers for the Event Group then the Ch0 for the Group1 would have to start at 0xFF3E0080 instead, not 0xFF3E0020.

  Please also go to the ADC userguide. How the buffers are partitioned is described. there. 

  If your EE really wants 32 buffers for event group and 24 buffers for Group1 then below is the HalCoGen setting and this will give you 0x0010001C written to the register. 

  

 2. See above explanation on how BNDA and BNDA are used in calculation.

 3. No, you can partition whatever number of buffers for each group. For example, you can configure 6 buffers for Event Group and 14 buffers for Group1 and the remaining (64-6-14)=44 will be reserved for Group2. BNDA in this case will be 3 and BNDB will be 10. 2*3=6 gives you 6 buffers for Event Group. 2*(10-3)=14 buffers for Group1. 

  4. See explanation in #1. BNDA is a pointer to the end of Event group or the beginning of Group1. The first buffer in event group will start at 0xFF3E0000. The starting address of Group1 buffers will depend on what BNDA is. You just shift left by two bits of the value of 2*BNDA to get the starting address of Group1.

Hi Charles, I understand things much better, thank you, however based on your screenshot above and explanation

It seems that HalCoGen does NOT display the BNDA and BNDB parameters that go into the register, but rather indicate how many 32-bit buffers one wants for Group Event, Group Event 1, and Group Event 2.

Taking the GUI literally on the above screenshot of yours would mean

BNDA: 16 (2 * 16 = 32 32-bit buffers)
BNDB: 12 (2 * (12-16) = -8 32-bit buffers
Register value: 0x0010000C

The register value in a generic sense based on my understanding is:
0x#### ####
[BNDA] [BNDB}

Plugging in 16 (0x0010) and 28 (0x001C) into the GUI yields lengths: 32 and 56. That is more than the 64 allowed. The GUI does not seem to honor the equation:

Group Event Length = 2 * BNDA
Group Event 1 Length = 2 * (BNDB - BNDA)
Group Event 2 Length = Remainder from 64

As I am concluding, the GUI wants you to enter the total number of buffers divided by 2 that you want in each group and the value that HalCoGen then writes to the register gets governed by the equation that you mentioned to me. That would make the GUI incorrect in labeling, as it should not say "BNDA:" and "BNDB:", but rather "Group Event / 2:" and "Group Event 1 / 2", possibly just "Group Event:" and "Group Event 1:" with the values of BNDA and BNDB being 2 other read only boxes that HalCoGen calculates on its own.

This reply is merely for completeness to whomever (me in the future) reads this post. I asked the EE how many 32-bit words for Group Event and Group Event 1, and here is the reply:

I do indeed want 24 ea 32 bit buffers, since there are 24 voltages to measure. (Actually, the thermocouple voltages won't be measured in this version, but read them anyway, to make it easier.)

Well, the answer was neither 8 or 32, but 24 for Group Event and 24 for Group Event 1 for a total of 48, which means 16 left over for Group Event 2. That gets an "oh well" on the memory math stated in the original requirement.