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Hi, I'm using SSI3 on EK-TM4C123GXL and noticed a very strange issue. After the line
SSIConfigSetExpClk(SSI3_BASE, CLOCK_RATE, SSI_FRF_MOTO_MODE_3,SSI_MODE_MASTER, 1200000,16);
The pin PB6 is stuck to logical one. And I cannot use it anymore.
During the SPI communication PB6 and PB7 act as SCK and CS along with pins PD0 and PD1! Even more - PORTB is not enabled at all.
Here is the init SPI3 code:
void initSPI3(void) { // attach spi master to SSI3 SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); /* * Configure the appropriate pins to be SSI instead of GPIO. The FSS (CS) * signal is directly driven */ GPIOPinConfigure(GPIO_PD0_SSI3CLK); GPIOPinConfigure(GPIO_PD2_SSI3RX); GPIOPinConfigure(GPIO_PD3_SSI3TX); GPIOPinConfigure(GPIO_PD1_SSI3FSS); GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_3| GPIO_PIN_2| GPIO_PIN_0); GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_1); /* * Set the SSI output pins to 4MA drive strength and engage the * pull-up on the receive line. */ GPIOPadConfigSet(GPIO_PORTD_BASE, GPIO_PIN_2, GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD_WPU); GPIOPadConfigSet(GPIO_PORTD_BASE, GPIO_PIN_0| GPIO_PIN_3| GPIO_PIN_1, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); // Configure the SSI3 port for mode 3, 16 bit data SSIConfigSetExpClk(SSI3_BASE, CLOCK_RATE, SSI_FRF_MOTO_MODE_3,SSI_MODE_MASTER, 1200000,16); SSIEnable(SSI3_BASE); }
CPU runs on 50MHz
Any ideas?
After an hour of investigation I've found out that PD0, PD1 are physically connected to PB6, PB7. How come? On all Tiva's I've got.
Hi,
Please download and read the LP user's manual - you will notice the existance of some zero ohm resistors connecting those pins - just remove them. You are not the only victim...
Petrei said:You are not the only victim...
But Petrei - hallowed vendor "Duly Notes" this issue - yet allows "more & more" hapless lemmings user-clients - to fall from this high cliff!
Not the best way to "Run a Railroad!" (and seemingly - only "outsiders" care/squawk...)