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First post on this this forum, thanks for your help.
I have a problem trying to setup the ENA pin functionality.
My HW setup is:
I have a simple project build with halcogen and I'm able to communicate in "Three-Pin Mode" (No care on ENA and CS) using SPI in compatibility mode to transfer one 16-bit word from SPI1 (master) to SPI3 (slave) in polling mode.
Now I want to do a step forward and use the ENA pin (no care on CS).
I set it as functional in halcogen to both SPI1 and SPI3 and enabled in the data format 0 of SPI1 "wait for enable". Now SPI1 waits for ENA, but SPI3 never pulls down ENA (I see it on oscilloscope) and the communication never takes place, SPI1 never drives the CLK. The master side (SPI1) seems ok because if i turn SPI3 ENA as GPIO and I pull it down manually, the communication takes place.
I even tried to write something in SPI3->DAT0, because I thought that It was waiting to have something ready in TX, but nothing changed.
Do you see anything wrong in my setup? Do you see any pitfall in this layout?
In this foggy situation I have two more doubts on documentation studying the TRM SPNU503B:
Thanks
Any answer? Primarily on the priority doubt...
Does the SPI machine somehow guarantees a priority between reception and transmission when I'm working without CPU intervention? (For example a DMA channel for reception and a DMA channel for transmission with potentially different wait timings)
What should I consider?
anyway let me now please!
Thanks