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TM4C1294NCPDT: Analog signal jots below ground on single ended ADC and analog comparator input configuration.

Genatco
Guru 55433 points
Part Number: TM4C1294NCPDT
Other Parts Discussed in Thread: EK-TM4C1294XL, INA282, INA240, , LM4120

EK-TM4C1294XL

Circuit & configuration : 3 single ended ADC analog inputs current monitors signal jots 200mv below ground in a cyclic loop. Same 3 amplified resistive gain reduced signals also feed 3 onboard digital comparators respectively the outputs feed 3 PWM0-M0nFault input trigger pins. Analog Digital comparator thresholds are set 14.4 amps maximum and have +VREFA rail as the voltage source for internal VREF resistor bridge. Actual detected digital running current (6.7-8.6 amps) roughly 5.8 amps below the digital comparators maximum trip point 3.6 amps and below the minimum trip point 12.2 amps where 13.3 amps ideal.  But.....

Issue: Random PWM faulting is occurring when respectively no over current threat exists.

1st remedy: Changed R41 (0R0) XLTM4C launch pad to R41=10kR0 to isolate and limit +VREFA  300na. Also added 0.01uf ceramic to ground at the +VREFA input pin.

Results: Far less random comparator trips resulted yet did not completely arrest the phantom faulting condition.

2nd remedy: Add 1nf capacitors directly across low side INA282 current monitor shunt resistors.

Results: Even less random analog comparator trips occurred yet did not completely arrest phantom faulting.

Suspecting comparator inputs jotting below ground has some effect on the internal +VREFA that reduces the minim trip threshold by 200mv or more but unclear as to why.

Question:

1. Please elaborate why random comparator trips occur when GNDA is at 0v0 potential or how signal below ground (single ended ADC) violates datasheet specifications?

2. Does signal jotting 200mv below ground cause TM4C errata when the INA282 current monitor can senses bipolar CMM up to -14v and GNDA is 0v0 potential?

3. INA240 claims -4v CMM and likely could reduce GNDA artifact and some PWM noise (dv/dt) input to analog comparators.

Any thoughts or suggestions how GNDA in production runs should be handled or how to test rig the XL launch pad to halt the phantom?

CH1: FET turns off then back on. CH2: INA282 monitors the current rise.

  • 0
    Guru 55433 points

    TM4C1294NCPDT data sheet VDDA/VDD note (a) seems to contradict EK-TM4C1294XL launch pad schematic has VDDA tied to VDD.
    Note: EK-TM4C1294XL has VDDA and VDD powered from the same source and should be separated but are not.

    27.3.1 VDDA
    a. To ensure proper operation, VDDA must be powered up before VDD if sourced from different supplies, or connected to the
    same supply as VDD. There is not a restriction on order for powering off.

  • 0 in reply to Genatco
    TI__Guru 72500 points
    BP101,
    I do appreciate your input. I don't see this as a contradiction. The requirement to power up VDDA before VDD only applies if the supplies are separate. The EK-TM4C129XL has VDDA tied to VDD so that requirement does not apply. Perhaps it would have been better if we worded it as: "To ensure proper operation, VDDA must be powered up before VDD, or VDDA must be connected to VDD. There is not a restriction on order for powering off."
  • 0
    TI__Guru 72500 points
    BP101,

    You are on the right track. The minimum analog comparator input voltage for proper operation is GNDA. When you drop below that voltage, you pull the internal GNDA down. That will pull the internal reference down which causes the comparator to trip. I suspect that the voltage is going lower than -200mV, but you would need to zoom in with the scope. You may need to add a low pass filter.
  • 0 in reply to Bob Crosby
    Guru 55433 points

    Hi Bob,

    Bob Crosby said:
    The requirement to power up VDDA before VDD only applies if the supplies are separate

    Thanks for clarifying the OR clause but does a precision regulator count as being a separate VDDA supply since precision voltage source LM4120 respectively exists after the +3v3 LDO on our custom PCB?

    Have VDDA and +VREFA tied together on custom PCB and both sourced from same +3v3 LDO regulator. This is so ADC can work with either the internal reference or an external precision reference determined by circuit population and or software configuration.

    What to do in case  VDD is powered up 1st when a precision voltage source is populated and uses +VREFA for VREFP source? 

    Why would a separate power source ever become an issue when required decoupling caps (Cf = 0.01/1.0uf parallel), thusly causes an unavoidable delay +VREFA even with single sourced power?

    The same power up condition VDD exists either power source VDDA so the OR note makes no sense. 

    Note: The EK-TM4C1294XL does not populate (Cf) on +VREFA and sets a bad example many this forum have copied, verbatim. 

  • 0 in reply to Bob Crosby
    Guru 55433 points

    Bob Crosby said:
    BP101,

    You are on the right track. The minimum analog comparator input voltage for proper operation is GNDA. When you drop below that voltage, you pull the internal GNDA down. That will pull the internal reference down which causes the comparator to trip. I suspect that the voltage is going lower than -200mV, but you would need to zoom in with the scope. You may need to add a low pass filter.

    I have seen it shoot even lower than -200mv but never catch it when the COMP trip event occurs. Perhaps the INA240 PWM rejection will stop some of the splash ringing when the phase FETs turns on/off. That (dv/dt) ringing event is much worse with the +24vdc switching supply than with 160vdc linear supply but INA output still shoots -200mv. 

    After some deductive reasoning it seems -200mv might actually be FET turn off (dv/dt) ringing but is delayed by scope triggers either channel so it seems to appear as a FET turn on event to the human brain.

    A real brain teaser for sure!