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TM4C1292NCPDT: QSSI Modes, advanced mode, Freescale SPI format continuous transfer timing

matthew reich
Prodigy 160 points
Part Number: TM4C1292NCPDT

Hello,

Chapter 17 of the TM4C1292 users Manual describes the QSSI.

Several questions:

For 8 bit frames, how does advanced mode (not bi- or quad- ) modes differ from legacy mode?  Are 'enhanced modes' per  17.3.4 the same as 'advanced mode'?

Clearly enhanced mode selects Feescale format.  Beyond that, paragraph 17.3.4 describes using the FSSHLDFRM bit of the SSICR1 register to configure SSInFss signaling.  Does the MODE bit field of sSICR1 have to select a mode other than Legacy to configure SSInFss signaling? 

Other than the restriction to 8 bit frames, how else does does Advanced SSI mode differ from legacy mode?

To operate in Advanced SSI mode requires SPO=0 and SHP=0, and Frescale SPI format.  Figure 17-5 describes this protocol.  But, neither this figure nor any other fully specifies the frame timing.  The figure shows an unspecified period in which SSInClk remains low between the LSB of one frame and the MSB of the next.  What is the timing for this mode?  What document specifies the timing?

Thanks.

m.r.

  • 0
    Guru 117855 points
    Excellently prepared & constructed post - Bravo!

    In advance of vendor response - might your "experimentation" provide (some) insight? (firm/I do not use 4C129 - thus "heavy lifting" falls upon you...)

    Your "Set-Up & Config." - to your liking - and then test - w/presentation of "scope caps" (while "attached" to a suitable QSSI slave (memory likely)) may prove of use (and/or confirmation) to vendor's effort...

    As always - insure that yours is the "latest/greatest" MCU data and that you've reviewed (latest) errata...