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TMS570LC4357: DCAN ECC Testing

Milin P.
Prodigy 110 points
Part Number: TMS570LC4357

Hi,

I have been reading about the DCAN recently and I am trying to test the DCAN RAM ECC functionality. I am not entirely clear on the SECDED mechanism. The desired functionality that we want is that on any ECC error (single or double), the ESM should be notified. We do not want to correct any ECC errors. So the questions I have:

1. Is the ECC checking enabled by default? If not, how is it enabled and is it the same thing as SECDED?

2. How do we inject a fault to test the ECC functionality. It seems like section 27.15.3 in the TRM should be the way to do this but no error was detected in my implementation.

Thanks,

Milin

  • 0
    TI__Guru**** 193086 points
    Hi Milin,

    1. The ECC can be enabled or disabled by PMD bit field in CAN Control Register. If SECDED is enabled, ECC bits will be automatically generated and checked. The ECC is disabled at default.

    2. With the ECCMODE field in the ECC Control and Status register the single-bit error correction can be enabled or disabled (default: enabled). In diag mode, the ECC error will not be reported to ESM.
  • 0 in reply to QJ Wang
    Prodigy 110 points
    I tried enabling the ECC by setting the PMD bit but that caused an ECC error on initialization. This was caused because the DCAN ram was not being initialized using the Memory Hardware Initialization registers. I got it working after I added that.
  • 0 in reply to Milin P.
    TI__Guru**** 193086 points
    Hi Milin,

    Great, it works. Memory initialization will initialize its memory based on its memory error checking scheme (ECC).