• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 30 subscribers
  • Views 665 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TMS570LC4357: Errata CORTEX-R5#7 (ARM ID-780125) question regarding usage of write-back memory with cache-ECC

TMS570LC4357: Errata CORTEX-R5#7 (ARM ID-780125) question regarding usage of write-back memory with cache-ECC

rp3
Prodigy 120 points
Part Number: TMS570LC4357

Hi, 

I am opening a related thread for the same topic since the last one has been locked.

I still haven't got a clear feedback on this matter, but I suppose ARM also didn't give any feedback on this Errata ; however I would really appreciate an answer to confirm the use of WB policy for cache memory on R5.

Here is the original question : 

The errata CORTEX-R5#7 (ARM ID-780125) suggests a work-around to avoid deadlock or data loss when using cache-ECC: setting the ACTLR.DBWR bit to 1.

It is unclear to me if additionnally to this work-around, the write-back attribute should or should not be used for the different memory regions of the TMS.

It is written that "This setting also disables generation of AXI bursts by the processor for Write-Through and Non-cacheable Normal memory, but not Write-Back memory."

So can I use the write-back attribute for SRAM, external memories, etc. ? or am I forced to use write-through attribute (which reduces significantly the performance of the cache) ?

 

It is confusing for me that the issue starts with "When Write-back cache is selected..." (so this mode seems to be the issue) and that the workaround paragraph explains the DBWR does not disable the AXI bursts for Write-back.

I really need to be sure if I can or cannot use the Write-back mode at all when the workaround is applied...

 

 

Thank you,

Regards,

RP

  • 0
    TI__Guru**** 192666 points
    Hi RP,

    The CORTEX-R5#7 erratum can be avoided by setting ACTLR.DBWR (bit [14]) to 1. But setting bit will disable the AXI burst operation for write-through noemal memory and no-cacheable normal memory. This setting will not disable the AXI burst for write-back normal memory.
  • 0 in reply to QJ Wang
    Prodigy 120 points

    Hi QJ,

    Thanks for your response, but this Erratum is ambiguous to me.

    As I understand, setting ACTLR.DBWR to 1 will not disable AXI burst for write-back memory. Yet, the Erratum was raised specifically for cases where the WB mode is selected.

    So, can I use WB mode safely after setting ACTLR.DBWR to 1 ?

    We already discussed this matter in the original topic. Aa I recall, you contacted ARM on this matter but never got an answer ?

    Thanks,

    RP

  • 0 in reply to rp3
    TI__Guru**** 192666 points
    Hello,

    1. Setting ACTLR.DBWR (bit [14]) to 1 will avoid this erratum
    2. Setting ACTLR.DBWR (bit [14]) to 1 will disable the AXI bursts for Write-Through normal memory and No-Cacheable normal memory
    3. Setting ACTLR.DBWR (bit [14]) to 1 will not affect the AXI bursts for Write-back normal memory
  • 0 in reply to QJ Wang
    Prodigy 120 points

    Hi QJ,

    Your support is very appreciated as this was an important subject for me.

    It is good to know that I can use WB mode with the work-around.

    Thanks,

    Regards,

    RP