• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Subscribers 30 subscribers
  • Views 693 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

VDD shorts

Genatco
Guru 55513 points
Part Number: TM4C1294KCPDT
Other Parts Discussed in Thread: REF2033, UCC27714

Connecting REF2033 output hot into VREF of analog comparator PIN0 (c0+ PC6) input seemed to reduce ADC sample noise in GUI scope widgets, also stopped USB0 client from sudden disconnects of PWM0 activity. However WDOG then reset MCU several times after, external VREF via 5k pot (+3v3/18k to AGND) set to 3.2v fewer DOG resets. 

The odd part ADC samples DC bus voltage reading several volts higher until PWM0 trigger speed increased from 1ms up to 80us. The shorted VDD MCU 2v LDO regulator pins and all other used pins show NO curve trace stressing.

Also removed +3v3 LDO with hot air, ground pin pad was slightly grey but 3v3 produced roughly same DC ripple (below capture) as EVM LDO regulator.  

The end result after MCU resets thus shorted VDD of an MCU being several months of testing on same PCB at DC bus voltages <100v. Failed MCU again removed from PCB (5x), sure enough VDD pins are shorted to GND, past was VBUS pin the culprit. The wonder of having 2oz plating on TQFP 128 pins, same PCB new MCU less a gold plated socket would be much faster!

New MCU installed - should REF2033 being used as analog comparator 3.2v VREF be causing VDD/VDDA mayhem? Did REF2033 output being connected direct to C0+ PC6 play some part of VDD shorting? 

  • 0
    Guru 55513 points
    BTW: There was/were 3v3 stand off 1ns reacting OnSemi TVS diode on VDD and C0+ VREF input. Any VDD transient >VBR (5v) should have been taken to DGND or AGND in the case of C0+ input.
  • 0 in reply to Genatco
    Guru 55513 points

    New MCU has same issue elevated voltage & temperature reading after POR when using REF2033 for external comparator C0+ threshold +3.2v. The REF2033 +3.2v output has 1k series resistor 22nf to AGND analog comparator pin PC6.  

    The original 5k pot threshold PC6 input divider had 10k to AGND  and was full turns open 5k to AGND, 15k total with pot. Effectively 1k from 3v3 into PC6 set threshold 2.9v. Later changed 10k to 18k setting threshold 3.29v when comparator tripped more often than being set 2.9v and WDOG was acting crazy.

    Setting the analog comparator threshold C0+ (PC6) above 3v seems to effect the internal VREF in VDDA tied to VDD. The shorted VDD reads 11.3 ohms GNDA pin 10 to VDD pin 7. Analog comparator internal VREF (ladder decoder) is disabled since external PC6 sets the C0+ threshold.

        MAP_ComparatorRefSet(COMP_BASE, COMP_REF_OFF);
  • 0 in reply to Genatco
    TI__Guru**** 181966 points
    Hi,
    I'm not sure why the watchdog reset comes into play here. Normally, the watchdog reset is triggered due to runaway code. If that is the case then I can only image the voltage supply must be out of the spec (i.e. less than 2.97V or greater than 3.63V). But in your scope, I don't see that.
  • 0 in reply to Charles Tsai
    Guru 55513 points
    Hi Charles,

    Agree since shorting VDDA via analog comparator using PC6 >3.2v caused the POR, only assumed watchdog was jumping in. It seems the analog comparator C0+ threshold can not be set >3v or it shorts VDD to GNDA.
  • 0 in reply to Genatco
    Guru 55513 points

    Again the symptom of PC6 being >3v are elevated idle ADC readings until PWM0 changes the trigger timing on the sequencer from 1ms to 40us center of count. Sort of what other posts indicated sequencer trigger timing effects amplitude of sample acquisitions but it may be more related to the internal VDDA=VREFP reference.

    Oddly when past years PC6 <3v threshold the ADC 1ms idle samples are the same as 40us samples.

  • 0 in reply to Genatco
    Guru 55513 points
    The other odd condition REF2033 connected to C0+ (PC6) corrected USB0 client disconnects from PWM0 activity. Very afraid to short another MCU from C0+ set >3v. The question is should C0+ >3v threshold be shorting VDD to GNDA or VDDA?
  • 0 in reply to Genatco
    Guru 55513 points

    PC6 connected back to pot via +3v3 threshold 2.5v and still had POR high DC bus voltage and MCU temperature measures. Not sure what has made that occur just like it did after connecting PC6 to REF2033 to set a higher fault threshold. Later today discovered one of three UCC27714 gate driver HO output has reverse path to HS pin, another bad gate driver :-(

    Have reported several times UCC27714 causes high inductive voltage peaks when HS shorts to HO drive. Months ago raised gate drive 130 ohms far above 4 amp peak current datasheet shows possible. Have to believe this gate driver was failed before moving PC6 to REF2033 for better noise isolation and peak C0+ trip points >2.9v.