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Original question:
Safety Demo on TMS570LS04x launchpad: NHET parity error triggered at unexpected line of code
I'm running parity error test on HTU1. I'm able to generate the parity error OK and it's correctly flagged by PEFT in the PAR. However, the PAOFF seems stuck at 0x001 and so when I compare with the actual faulted address "#define htu1RAMLocVar ((uint32)0xFF4E0004U)" for SL API, I get an address mismatch and the test fails. Th
The PAOFF in HTU1 is stuck at 0x001 after Halcogen sysInit() (specifically after periphInit() in system.c which merely releases the peripherals from reset). Because of this I can't get the correct parity error address even though PEFT is set on error as expected. I've tried reading the entire 32-bit PAR as suggested by the TRM but that doesn't unfreeze it. The TRM has a note that "The Parity Error Address bits will not be reset, neither by PORRST nor by any other reset source." How do I get around this?
I believe I'm seeing similar behavior with DMA parity test although that only fails on the first test - subsequent tests are OK. Any thoughts will be greatly appreciated.
The PAOFF is still 0x001 after this change. I confirmed that the parity bit at 0xFF4E0204U is flipped to a "1" after this change but my test still didn't work.
Before executing the line below
/* Cause parity error */
ramRead = (*htuRAMLoc);with htuRAMLoc = 0xFF4E0004. The PAR content is
PEFT = 0
PAOFF = 0x001
Immediately after executing ramRead = (*htuRAMLoc); line, the PEFT = 1 but PAOFF stays the same. See screenshot below.
Is there anything else I should try?
BTW: I'm not working with HTU2 now, but for HTU2 should #define htu2RAMParLoc ((volatile uint8 *)0xFF4C020BU) be also changed to #define htu2RAMParLoc ((volatile uint8 *)0xFF4C0208U) if HTU1 is a bug?
#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1)) #define htu2RAMParLoc ((volatile uint8 *)0xFF4C020BU) #else #define htu2RAMParLoc ((volatile uint8 *)0xFF4C0208U) #endif #define htu2RAMLocVar ((uint32)0xFF4C0008U) #define htu2RAMLoc ((volatile uint32 *)0xFF4C0008U) #endif
Hello Sir,
I repeated HTU1 parity test many times on RM48 HDK, and I got the correct PAROFF for all the tests:
1. To generate parity error for data bit 0 of 0xFF4E0000, the address offset of the parity error is 0x03
2. To generate parity error for data bit 8 of 0xFF4E0000, the address offset of the parity error is 0x02
3. To generate parity error for data bit 16 of 0xFF4E0000, the address offset of the parity error is 0x01
4. To generate parity error for data bit 0 of 0xFF4E0004, the address offset of the parity error is 0x07
5. To generate parity error for data bit 16 of 0xFF4E0004, the address offset of the parity error is 0x05
Any questions?
I will try the SDL later.
Just check the MPU setting of the SDL example code. The MPU for 0xFF000000 memory region is device mode, please change it to strongly-ordered mode:
Hello Sir,
Did HTU1 RAM parity test with SDL, it works fine:
BTW, htu1RAMParLoc ((volatile uint8 *)0xFF4E0207U) in SDL is correct. I didn't notice it is uint8 last time.
