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Tool/software: Code Composer Studio
Hi,
We are using TM4C129ENCPDT with CY14B108K NVRAM. We have made a PCB prototype interfacing the controller and the NVRAM IC. The connections are made according to the Host Bus Mode (8 bit) of the EPI peripheral. In the software side, I don't know how to access the memory to read and write data but I did the EPI configuration part as per the example code in the Peripheral Driver Library datasheet.
CY14B108K NVRAM has 1 MByte (1024K x 8) of memory. So 20 Address Lines and 8 data lines are needed. The LSB 8 bits of the address lines are multiplexed with data lines. So a D Latch Register IC is used to de mux address and data, which is controlled by the ALE signal of the EPI peripheral.
// The Multiplexed 8 bits of Address-Data bits (AD0 to AD7) and remaining lines (A8 to A19)
MAP_GPIOPinConfigure(GPIO_PK0_EPI0S0);
GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_0); //AD0
MAP_GPIOPinConfigure(GPIO_PK1_EPI0S1);
GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_1); //AD1
MAP_GPIOPinConfigure(GPIO_PK2_EPI0S2);
GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_2); //AD2
MAP_GPIOPinConfigure(GPIO_PK3_EPI0S3);
GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_3); //AD3
MAP_GPIOPinConfigure(GPIO_PC7_EPI0S4);
GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_7); //AD4
MAP_GPIOPinConfigure(GPIO_PC6_EPI0S5);
GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_6); //AD5
MAP_GPIOPinConfigure(GPIO_PC5_EPI0S6);
GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_5); //AD6
MAP_GPIOPinConfigure(GPIO_PC4_EPI0S7);
GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_4); //AD7
MAP_GPIOPinConfigure(GPIO_PA6_EPI0S8);
GPIOPinTypeEPI(GPIO_PORTA_BASE, GPIO_PIN_6); //A8
MAP_GPIOPinConfigure(GPIO_PA7_EPI0S9);
GPIOPinTypeEPI(GPIO_PORTA_BASE, GPIO_PIN_7); //A9
MAP_GPIOPinConfigure(GPIO_PG1_EPI0S10);
GPIOPinTypeEPI(GPIO_PORTG_BASE, GPIO_PIN_1); //A10
MAP_GPIOPinConfigure(GPIO_PG0_EPI0S11);
GPIOPinTypeEPI(GPIO_PORTG_BASE, GPIO_PIN_0); //A11
MAP_GPIOPinConfigure(GPIO_PM3_EPI0S12);
GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_3); //A12
MAP_GPIOPinConfigure(GPIO_PM2_EPI0S13);
GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_2); //A13
MAP_GPIOPinConfigure(GPIO_PM1_EPI0S14);
GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_1); //A14
MAP_GPIOPinConfigure(GPIO_PM0_EPI0S15);
GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_0); //A15
MAP_GPIOPinConfigure(GPIO_PL0_EPI0S16);
GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_0); //A16
MAP_GPIOPinConfigure(GPIO_PL1_EPI0S17);
GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_1); //A17
MAP_GPIOPinConfigure(GPIO_PL2_EPI0S18);
GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_2); //A18
MAP_GPIOPinConfigure(GPIO_PL3_EPI0S19);
GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_3); //A19
// Accd. to the " HB8 Signal (MODE=ADMUX) " , EPI0S28 is said to be configured as OE* and EPI0S29 is said to be configured as WR* and EPI0S30 as ALE signal MAP_GPIOPinConfigure(GPIO_PB3_EPI0S28);
GPIOPinTypeEPI(GPIO_PORTB_BASE, GPIO_PIN_3); //Output Enable (Active Low pin)
MAP_GPIOPinConfigure(GPIO_PP2_EPI0S29);
GPIOPinTypeEPI(GPIO_PORTP_BASE, GPIO_PIN_2); // Write Enable (Active Low pin)
MAP_GPIOPinConfigure(GPIO_PP3_EPI0S30);
GPIOPinTypeEPI(GPIO_PORTP_BASE, GPIO_PIN_3); // ALE signal given to D latch register IC
/*
* The following two pins are input to a 2x4 Decoder IC. It is configured in such a way that the CS* pin of NVRAM IC
* is always held at Logic 0
*/
GPIOPinWrite(GPIO_PORTL_BASE,GPIO_PIN_4, 0x00);
GPIOPinWrite(GPIO_PORTB_BASE,GPIO_PIN_2, GPIO_PIN_2);
// Enable the EPI module.
SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);
// Wait for the EPI module to be ready.
while(!SysCtlPeripheralReady(SYSCTL_PERIPH_EPI0))
{
}
// Set the EPI divider.
EPIDividerSet(EPI0_BASE, 0);
// Select SDRAM mode.
EPIModeSet(EPI0_BASE, EPI_MODE_HB8);
EPIConfigHB8Set(EPI0_BASE,
EPI_HB8_MODE_ADMUX | //sets data and address muxed,
EPI_HB8_WRWAIT_3 | //sets write wait state to 2 EPI clocks.
EPI_HB8_RDWAIT_3 | //sets read wait state to 2 EPI clocks.
EPI_HB8_CLOCK_GATE_IDLE| // holds the EPI clock low when no data is available to read or write.
EPI_HB8_CSCFG_ALE, //sets address latch active low.
1); // the maximum number of external clocks to wait if a FIFO ready signal is
//holding off the transaction.
EPIAddressMapSet(EPI0_BASE,
EPI_ADDR_PER_SIZE_16MB |
EPI_ADDR_RAM_BASE_6);
while(HWREG(EPI0_BASE + EPI_O_STAT) & EPI_STAT_INITSEQ)
{
//
// Wait for initialization to complete.
//
}
If I run the code, there is no issues. I control comes out of the above while loop. But I don't know how to read/write data into the NVRAM IC. I tried the example code given in the Peripheral Driver Library datasheet, but I couldn't understand it.
In the EPIAddressMapSet configuration, if I keep the variable as EPI_ADDR_RAM_BASE_NONE, code goes into the Fault Interrupt. If I keep it as EPI_ADDR_RAM_BASE_6, it is good.
My application needs to write and read a structure into the NVRAM.
Kindly guide me to read and write a simple data into the memory.
Thank You for your time.
