TM4C129ENCPDT: EPI Refresh Configuration

Hello (again)

I'm interfacing to an 8MB / 64Mbit SDRAM and was hoping someone could confirm my understanding of the refresh counter value that is passed to EPIConfigSDRAMSet() please.

I have a 25MHz XTAL and using the PLL to generate a 120Mhz system clock frequency.

I set the divider of 1 so the EPI Clk = (120MHz / (((1 / 2) + 1) * 2) = 40MHz It states in the docmentation that a divider value of 1 results in an EPI clock rate of half the system clock 40MHz != 120MHz / 2 but instead a third of the system clock.

Using 40MHz I get:

RFSH = 64000 / 4096 = 15.625 / 0.025 = 625

My call to EPIConfigSDRAMSet() is therefore:

MAP_EPIConfigSDRAMSet(EPI0_BASE, (EPI_SDRAM_CORE_FREQ_30_50 | EPI_SDRAM_FULL_POWER | EPI_SDRAM_SIZE_64MBIT), 625);

However if it were 60MHz (120MHz / 2)

RFSH = 64000 / 4096 = 15.625 / 0.016 = 937

And my call to EPIConfigSDRAMSet() would now be:

MAP_EPIConfigSDRAMSet(EPI0_BASE, (EPI_SDRAM_CORE_FREQ_50_100 | EPI_SDRAM_FULL_POWER | EPI_SDRAM_SIZE_64MBIT), 937);

The interface is configured sufficiently that I can run a march test over the entire SDRAM using either configuration which worries me especially given the warning that "If a number larger than allowed is used, the SDRAM is not refreshed often enough, and data is lost".

Thanks,

HL