TM4C129ENCPDT: EPI General Purpose Mode EPI_WR Polarity

Hi,

  Please refer to the datasheet below for general purpose mode. 

■ Use of the RD and WR outputs is controlled by the RW bit in the EPIGPCFG register. For interfaces
where the direction is known (in advance, related to frame size, or other means), these strobes
are not needed. For most other interfaces, RD and WR are used so the external peripheral knows
what transaction is taking place, and if any transaction is taking place.
■ Separation of address/request and data phases may be used on writes using the WR2CYC bit in
the EPIGPCFG register. This configuration allows the external peripheral extra time to act.
Address and data phases must be separated on reads. When configured to use an address as
specified by the ASIZE field in the EPIGPCFG register, the address is emitted on the with the
RD strobe (first cycle) and data is expected to be returned on the next cycle (when RD is not
asserted). If no address is used, then RD is asserted on the first cycle and data is captured on
the second cycle (when RD is not asserted), allowing more setup time for data.
Note: When WR2CYC = 0, write data is valid when the WR strobe is asserted (High). When
WR2CYC = 1, write data is valid when the WR strobe is Low after being asserted (High).
For writes, the output may be in one or two cycles. In the two-cycle case, the address (if any) is
emitted on the first cycle with the WR strobe and the data is emitted on the second cycle (with
WR not asserted). Although split address and write data phases are not normally needed for
logic reasons, it may be useful to make read and write timings match. If 2-cycle reads or writes
are used, the RW bit is automatically set.