Hi,
I used to work with the EPI bus in HB16 mode but I would like to try the General Purpose mode to gain speed between FPGA and TM4C.
Here's the EPI configuration:
volatile unsigned short * epiFPGA = (unsigned short *)0xA0000000;
#define EPI_PORTA_PINS GPIO_PIN_7 | GPIO_PIN_6 //
#define EPI_PORTB_PINS GPIO_PIN_3 | GPIO_PIN_2 //
#define EPI_PORTC_PINS GPIO_PIN_7 | GPIO_PIN_6 | GPIO_PIN_5 | GPIO_PIN_4 //
#define EPI_PORTD_PINS 0x00 //
#define EPI_PORTE_PINS 0x00 //
#define EPI_PORTF_PINS 0x00 //
#define EPI_PORTG_PINS GPIO_PIN_1 | GPIO_PIN_0 //
#define EPI_PORTH_PINS GPIO_PIN_3 | GPIO_PIN_2 | GPIO_PIN_1 | GPIO_PIN_0 //
#define EPI_PORTJ_PINS 0x00
#define EPI_PORTK_PINS GPIO_PIN_5
#define EPI_PORTL_PINS GPIO_PIN_4 | GPIO_PIN_3 | GPIO_PIN_2 | GPIO_PIN_1 | GPIO_PIN_0 //
#define EPI_PORTM_PINS GPIO_PIN_3 | GPIO_PIN_2 | GPIO_PIN_1 | GPIO_PIN_0 //
#define EPI_PORTP_PINS GPIO_PIN_3 | GPIO_PIN_2 //
EPI_Init()
{
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);
ROM_GPIOPinConfigure(GPIO_PA6_EPI0S8);
ROM_GPIOPinConfigure(GPIO_PA7_EPI0S9);
GPIOPinTypeEPI(GPIO_PORTA_BASE, EPI_PORTA_PINS);
ROM_GPIOPinConfigure(GPIO_PB2_EPI0S27);
ROM_GPIOPinConfigure(GPIO_PB3_EPI0S28);
GPIOPinTypeEPI(GPIO_PORTB_BASE, EPI_PORTB_PINS);
ROM_GPIOPinConfigure(GPIO_PC4_EPI0S7);
ROM_GPIOPinConfigure(GPIO_PC5_EPI0S6);
ROM_GPIOPinConfigure(GPIO_PC6_EPI0S5);
ROM_GPIOPinConfigure(GPIO_PC7_EPI0S4);
GPIOPinTypeEPI(GPIO_PORTC_BASE, EPI_PORTC_PINS);
ROM_GPIOPinConfigure(GPIO_PG0_EPI0S11);
ROM_GPIOPinConfigure(GPIO_PG1_EPI0S10);
GPIOPinTypeEPI(GPIO_PORTG_BASE, EPI_PORTG_PINS);
ROM_GPIOPinConfigure(GPIO_PH0_EPI0S0);
ROM_GPIOPinConfigure(GPIO_PH1_EPI0S1);
ROM_GPIOPinConfigure(GPIO_PH2_EPI0S2);
ROM_GPIOPinConfigure(GPIO_PH3_EPI0S3);
GPIOPinTypeEPI(GPIO_PORTH_BASE, EPI_PORTH_PINS);
ROM_GPIOPinConfigure(GPIO_PK5_EPI0S31);
GPIOPinTypeEPI(GPIO_PORTK_BASE, EPI_PORTK_PINS);
ROM_GPIOPinConfigure(GPIO_PL0_EPI0S16);
ROM_GPIOPinConfigure(GPIO_PL1_EPI0S17);
ROM_GPIOPinConfigure(GPIO_PL2_EPI0S18);
ROM_GPIOPinConfigure(GPIO_PL3_EPI0S19);
ROM_GPIOPinConfigure(GPIO_PL4_EPI0S26);
GPIOPinTypeEPI(GPIO_PORTL_BASE, EPI_PORTL_PINS);
ROM_GPIOPinConfigure(GPIO_PM0_EPI0S15);
ROM_GPIOPinConfigure(GPIO_PM1_EPI0S14);
ROM_GPIOPinConfigure(GPIO_PM2_EPI0S13);
ROM_GPIOPinConfigure(GPIO_PM3_EPI0S12);
GPIOPinTypeEPI(GPIO_PORTM_BASE, EPI_PORTM_PINS);
ROM_GPIOPinConfigure(GPIO_PP2_EPI0S29);
ROM_GPIOPinConfigure(GPIO_PP3_EPI0S30);
GPIOPinTypeEPI(GPIO_PORTP_BASE, EPI_PORTP_PINS);
// General Purpose Init
ROM_EPIDividerSet(EPI0_BASE, 0x00010001); // 1/2 (System) = 120MHz * 0.5 = 60MHz
ROM_EPIModeSet(EPI0_BASE, EPI_MODE_GENERAL); // General Purpose
ROM_EPIConfigGPModeSet(EPI0_BASE, EPI_GPMODE_CLKPIN | EPI_GPMODE_ASIZE_12 | EPI_GPMODE_DSIZE_16, 1, 1);
ROM_EPIAddressMapSet(EPI0_BASE, EPI_ADDR_PER_SIZE_16MB | EPI_ADDR_PER_BASE_A);
}
Then in the main loop, I access the EPI data in a "for" loop :
#define FPGA_PORT epiFPGA[0x11]
g_sBuffer[0] = 0;
for (i= 1; i<20;i++) // Fill up with incrementing data
g_sBuffer[i] = (g_sBuffer[i-1] +1);
for (i= 0; i<20;i++) // Write it to the FPGA
FPGA_PORT = g_sBuffer[i];
There is probably something I am missing in the config but the Write frequency is somewhat slower than I expected. The time between reads varies from 800ns to 1.7us. The printscreen shows what I mean, first signal is EPI Data 0 and is toggled every write (that works)...:
EPI clock runs properly at 60MHz, there are really some long delays between Writes (or reads, have the same effect) that I cannot explain.
I disabled interrupts and it didn't change anything. By default should be the "Ready" signal disabled so I don't see what could be delaying Read or Write between each "for" cycle.
Thanks in advance for your help!
asdasdasdasd#define DTI_STATUS epiFPGA[0x11]