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TMS570LC4357: STC selftest via SafeTI Diagnostic Library

Adama
Intellectual 310 points
Part Number: TMS570LC4357

Hello,

When performing SL_SelfTest_STC(), of the SafeTI Diagnostic Library 2.4.0, with parameter “STC1_COMPARE_SELFCHECK” and following configurations :

      sl_stcREG1->STCSEGPLR = C_SEGMENT0;

                           stcSelfTestConfig.stcClockDiv       = 0;          

                           stcSelfTestConfig.intervalCount     = 1;          

                           stcSelfTestConfig.restartInterval0 = TRUE;        

                           stcSelfTestConfig.timeoutCounter   = 0xFFFFFFFF;  

the SL_SelfTest_Status_STC() returned status is “ST_FAIL”, with STCGSTAT = 0x500 and STCFSTAT = 0.

 

Can you indicate the issue when executing STC1_COMPARE_SELFCHECK with previous configurations ?

 

Best Regards,

  • 0
    TI__Guru**** 197036 points

    Hello Adama,

    The maximum clock rate for the self test is 110MHz. The STCCLK is divided down from the CPU clock. If the CPU clock is 300MHz, the STC clock divider (STCCLKDIV) is 2  (300/3=100MHz < 110MHz).

  • 0 in reply to QJ Wang
    Intellectual 310 points

    Hello,

    Thanks for your answer.

    My CPU clock is effectively 300 MHz, but setting "stcSelfTestConfig.stcClockDiv = 2" or a little greater gives the same result.

    How to run the test with interval count to 1 in STCGCR0 and, SELF_CHECK_KEY and FAULT_INS enabled in the STCSCSCR ?

    Best Regards,

  • 0 in reply to Adama
    TI__Guru**** 197036 points

    Hello Adama,

    I didn't use the SDL for STC selftest before. You can try SCT test without using the SDL:

    1. HL_systemREG2->STCCLKDIV = 0x02020000U;

    2. HL_stcREG->STCGCR0 = 0x00010001U; /* test interval, 1*/

    3. HL_ stcREG->STCSCSCR = 0x1AU; //enable

    4. HL_ stcREG->STCTPR = 0xFFFFFFFFU; //timeout

    5. for (i=0; i<(32; i++)      { /* Wait */ }

    6. HL_ stcREG->STCGCR1 = 0xAU; //enable selftest

    7. asm(" WFI");

    7. asm(" NOP");

     

    After test, please check the STCGSTAT register and STCFSTAT register.

    8. asm(" NOP");

    9.. asm(" NOP");

     

  • 0 in reply to QJ Wang
    Intellectual 310 points

    Hello QJ Wang,

    The test fails with STCGSTAT = 0x503 and STCFSTAT = 3.

    Are there any error registers to clear before to run the STC selftest ?

    Best Regards,

  • 0 in reply to Adama
    TI__Guru**** 197036 points

    Hello,

    SEG0_CORE_SEL is used to select cores for testing. The default is 0x00 which selects both core 1 and core 2 for self-test in parallel. This device has only 1 lock-step core. Please change this value to 0x5 to test core 1 only.

  • 0 in reply to QJ Wang
    Intellectual 310 points

    Hello,

    Thank you for this information.

    After appliying this correction, the result is a success  if STCSCSCR = 0xA and not 0x1A.

    Can you explain the influence of FAULT_INS enable (stuck-at-fault) in this selftest ? Is it relevant to disable FAULT_INS ?

    Best Regards,

  • 0 in reply to Adama
    Intellectual 310 points

    Do you have a functionnal example with FAULT_INS enabled (for the TMS570LC43) or indicate possible causes of the failure of your example ?

  • 0 in reply to Adama
    TI__Guru**** 197036 points

    Adama,

    I am sorry for late response. Setting FAULT_INS is to inject fault for STC selftest, and setting SELF_CHECK_KEY to 0x5 is enable the STC selftest. If those two fields are cleared, CPU selftest will be performed.

    When FAULT_INS=1, and SELF_CHECK_KEY=0x5, the STCGSTAT should be 0x503 and STCFSTAT should be 1 (if SEG0_CORE_SEL = 0x50A).

    Your test result on Nov 27th is correct.