• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 30 subscribers
  • Views 734 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

CCS/TMS570LC4357: eCAP interrupt execution

CCS/TMS570LC4357: counter and clock functions in ePWM and eCAP example provided inside HCG

Lu Zheng
Intellectual 565 points
Part Number: TMS570LC4357

Tool/software: Code Composer Studio

Dear experts, 

I am exercising the example_etpwm_ecap exercise inside HCG 04.07.01, just few questions that could help me to understand the clock and counter better.

1. is it correct that, the marked in yellow config. in 1st and 2nd pic is to synchronize between generated-pulse from ePWM and captured-pulse from eCAP?

2. if Q1 answer is yes, is the config in pic 2 to send this sync clk to eCAP?

    

3. Are the loading and stop in the following pic on the same timeline synchronized as ETPWM1SYNCO (so basically reading the same timeline given by ePWM or still reading eCAP timeline but synchronized with ePWM ) ?

4. for quesitons 3, I am curious if I tick "reset counter after capture3", which counter has been reset and what will be the impact on CEVT3 interrupt ?

Thanks a lot for help.

  • 0
    TI__Guru**** 196776 points

    Hello Lu,

    1. No. The TBCLKSYNC bit allows users to globally synchronize all enabled ePWM modules (totally 7 PWM modules on LC4357) to the time-base clock (TBCLK). When set, all enabled ePWM module clocks are started with the first rising edge of TBCLK aligned. ETPWM1SYNCO in 2nd Figure is to output this sync signals on terminal A4. This signal (ETPWM1SYNCO) is also fed to eCAP1 module for synchronization if it is enabled (normally used for APWM).

    2. ETPWM1SYNCO is fed to eCAP1 whatever the terminal A4 is used for.

    3. This defines the qualified event: CEVT3 (3rd rising edge). I don't think it is related to syno signal.

    4. "reset counter after capture3" : The 32-bit counter value is captured first, then it is reset to 0 by LD3 signal with your configuration. This doesn't affect the CEVT3 interrupt.