TMS320F28377D: CPU cycles wait upon simulateneous access by CPU1 and CPU2 to MSGRAM

Hi,

I know from another question I raised in the past that the MSGRAM between CPU2 and CPU1 and not double ports and that there is an arbitration.

To document our software worst case analysis, I need to know the number of CPU cycles during which a given CPU access can be delayed if both CPU try to access at the same time.

Are we speaking of one CPU cycle ? or more than that due to the internal bus design ?

Thanks,

Regards

Clément