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TMS320F28377D: The question of high speed SPI slave mode.

Luke Chen
Expert 5090 points
Part Number: TMS320F28377D

Hi champs,

In SPI slave mode, when one data word is received/transmit, it needs time for DSP to move SPIDAT to SPIRXBUF and then load data into SPIDAT from SPITXBUF.

If SPI host needs to send multiply words to DSP (SPI slave), is there specific needed time delay between SPI data words so that DSP is able to complete internal data transfer first?

In SPI high speed mode, if we say LSPCLK is 200 MHz, SPICLK is 50 MHz and data word length is 16-bit. When SPI host sends 32 bits SPI clock try to read out 32-bit data from DSP, then DSP will have about 4 cycles to complete internal data transfer and ready to output 17th data bit when SPI clock arrives, is it possible DSP outputs 17th data bit in time without problem?

Regards,

Luke 

  • 0
    TI__Mastermind 27981 points

    Luke,

    Actually, the sample rate (i.e. frequency of SPI characters) is 50Mbps / (16 bits/char) = 3.1M char/sec. For a 200MHz CPU like F2837x, that is about 64 cycles for it to move 1 character to/from the SPI registers. I think in this scenario is imperative to use the SPI FIFO mode and leverage the DMA for data movement. 

  • 0 in reply to Gus Martinez
    TI__Expert 5090 points

    Gus,

    Yes, my customer is using SPI FIFO and DMA for his use case.

    Do you mean it will need about 64 cycles for SPI module to move data word from SPIDAT to SPIRXBUF and load data from SPITXBUF to SPIDAT?

    If this is the case, when SPI host keep sending 50 MHz SPI clock, then DSP doesn't have enough time to compete internal data transfer after receiving one data word and ready to receive next data word, right?

    Regards,

    Luke

  • 0 in reply to Luke Chen
    TI__Mastermind 21000 points

    Hi Luke,

    Yes I believe you are correct in your line of reasoning. This is also why you should try to utilize FIFO mode with DMA to handle the data transfers as Gus suggested. Feel free to reference the description in the device TRM section 18.3.8 SPI DMA Transfers as well.

    Regards,

    Allison

  • 0 in reply to Allison Nguyen
    TI__Expert 5090 points

    Allison,

    If SPI host sends out 32 bits SPI clock at 50MHz, then DSP doesn't have enough time to respond the second 16-bit data word even we use FIFO and DMA function, since DSP needs time to do internal data transfer.

    The way to solve this problem is to limit the length of data word of SPI host, the maximum data word length is 16-bit, if we configure SPI communication frequency to 50MHz.

    Is it correct?

    Regards,

    Luke

  • +1 in reply to Luke Chen
    TI__Mastermind 21000 points

    Hi Luke,

    Yes, the SPI is optimized for 16-bit data size. Limiting the length of data word is a good way to help the issue. In general, the max data rate depends on the data size (as you are describing) & efficiency of the transfers within the device- the latter of which can be impacted by the SPI FIFO use and CPU/DMA MIPs availability/how you architect your code.

    Regards,

    Allison