TMS320F28388S: If enable valley switching, DCEVTFILT is synchronous output or asynchronous output?

Hi Echo,

Echo Yu said:

1. My understanding is that when enabling valley switching, DCEVTFILT is synchronous output. Then, in Figure 26-52. DCxEVT1 Event Triggering, if I set DCxCTL[EVT1SRCSEL] 1 to select DCEVTFILT, I notice there is sync logic after the EVT1SRCSEL mux, will the sync logic filter out the DCEVTFILT signal from valley switching? 

You do not want to select the sync'ed path after enabling the valley switching. Yes, the sync logic will filter out the DCEVTFILT signal.

You can test this using our ePWM example 6 CCS project. ePWM1B is using DCBEVT1 to force ePWM output low and adding a delay to the DCFILT signal by a software defined DELAY value. If you set DCBCTL[EVT1SRCESEL] = 0, (SYNC path) the DCEVTFILT does not get delayed and is filtered out. 

Echo Yu said:

2. In T1SEL, DCEVTFILT is output from valley switching or from event filtering(async after blank window filtering)? 

This is dependent on what is chosen in DFCTL[EDGEFILTSEL].

Echo Yu said:

3. In T1sel, following signals are level sensitive signals, how do they work on AQ PWM? Is PWM  toggling on the edge of these signals or PWM is always toggling when these signals is HIGH? 

If you configure your T1 AQ event to toggle and your digital compare event signal is still active then your PWM signals will NOT always toggle while the signals stay high until the next DCx event occurs.

For example:

If you have ePWMxA T1's AQ event to toggle, and you configure your Digital Compare event 1A's condition to be when DCxH is high. IF the digital compare 1A event stays high, the AQ event will not toggle continuously. Only on the rising edge of the DCEVT1 high signal, will the PWM output toggle.

Best,

Ryan Ma