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Original question:

TMS320F28388D: Combine SPI and CLB (Configurable Logic Block) to Read Simultaneously from Two Slaves

TMS320F280039C: Using CLB exclusively to read SPI data

K Pruthvi Raaj
Prodigy 70 points
Part Number: TMS320F280039C
Other Parts Discussed in Thread: ADS7853

Using a LAUNXL-F280039C, I wish to read data from ADS7853 through SPI but I want it to do it through CLB. I have a clock on SPIA which I can route it to CLB and a chip select on GPIO. My SPIA Use Case is set to CUSTOM and I am using everything except PTE. This is being done by GPIO as mentioned earlier. Due to hardware constraint in the project I wish to read the data through CLB to have minimal use of the CPU core and dump the data so read in a register and later read it from there. 

Is this something that is possible to do? Please let me know the configurational changes that need to be done to do this.

  • 0
    TI__Mastermind 28220 points

    Hello,

    Have you considered using SPI with DMA to move the data to a buffer without CPU intervention? What is your motivation/need to use CLB? The DMA is able to read the SPI RX FIFO and transfer the data without CPU intervention.

    Thank you,

    Luke

  • 0 in reply to Luke Jones
    Prodigy 70 points

    It is due to a hardware constraint in the design of PCB that has caused this. We intend to use CLB and the design has been made accordingly.

    Would be glad to know if there is anything on the original question

  • +1 in reply to K Pruthvi Raaj
    TI__Mastermind 28220 points

    If my understanding is correct, this hardware constraint restricts the pins you can use for SPI communication, correct? Is that why you are reproducing a SPI peripheral using the CLB?

    There is also the option to override the SPI RX signal using the CLB using the CLB output override function. You could read any pin using CLB input xbar, select the CLB Input XBAR in the CLB input mux, and send this signal to a CLB output that could override one of the SPI pins. The following table from the TRM lists the signals that can be overridden with the CLB:

    This would require a much less complicated CLB configuration. If you do not want CPU intervention, the DMA will be required to move data out of the SPI buffer regardless, so I would recommend this approach.

    Data can be written from the R0 register to the SPI RX FIFO by configuring an event to push to the FIFO in the CLB_SPI_DATA_CTRL_HI.STRB bit field. The HLC events are listed in the "HLC Event List" table.

    Thank you,

    Luke

  • 0 in reply to Luke Jones
    Prodigy 70 points

    Hello Luke,

    I understood that output override is what needs to be used here. However, I am not getting how exactly would you read in data from any GPIO. Like, where is the data stored, is it in some buffer, or a register?

    Would be great if you could elaborate on this.

    Also, just to add, due to the hardware constraint only clock and PICO and CLK is used in the custom SPIA setup. Chip select is currently being done through a GPIO and POCI is hopefully done by overriding pins.

  • 0 in reply to K Pruthvi Raaj
    TI__Mastermind 28220 points

    The CLB Input XBAR doesn't exactly "read" the GPIO. It is a mux whose inputs consist of GPIOs. You can select any GPIO by configuring the CLB Input XBAR mux.

    Let me know if you have additional questions.

    --Luke