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ezDSP F28335, XINT to external RAM, address bus pin layoutHi

In regard to schematic of SRAM (IS61LV6416/L) connection to F28335 for ezDSP F28335, I concern the way the address from F28335 connects to SRAM

XA0 to XA8  connect to A0 to A8 which is fine

XA9 connect to  A11

XA10 connect to A12

........

XA16 connect to A9

Is there reason for doing that?

Should I implement linear address from XA0 to XA16 to A0 to A16