Jitter on ePWM channel B when using High resolution

Hi Maulik,

Are you using High resolution dead band? Can you share complete EPWM configuration?

-Bharathi.

Dear Bharathi,

Thank you for response. No, I am not using High resolution dead band. But, i have configured it in half-clocking mode to get 2.5 ns resolution at 200MHz.

I am following below step to generate HRPWM for my H-bridge topology. System clock and PWM clock both working at 200MHz.

step 1:
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;

step 2:
// Setup TBCLK
EPwm6Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm6Regs.TBPRD = 196;
EPwm6Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm6Regs.TBCTR = 0x0000; // Clear counter

EPwm6Regs.TBCTL.bit.FREE_SOFT = 3;
EPwm6Regs.TBCTL.bit.PRDLD = 0;
EPwm6Regs.TBCTL.bit.CLKDIV = 0; //no division yet
EPwm6Regs.TBCTL.bit.HSPCLKDIV = 0;
EPwm6Regs.TBCTL.bit.SWFSYNC = 0;

EPwm6Regs.TBCTL.bit.SYNCOSEL = 1;
EPwm6Regs.TBCTL.bit.PRDLD = 0;
EPwm6Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading

// Setup TBCTL2
EPwm6Regs.TBCTL2.bit.SYNCOSELX = 0;
EPwm6Regs.TBCTL2.bit.PRDLDSYNC = 0;

// Setup shadow register load on ZERO
EPwm6Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm6Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm6Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm6Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

// Set Compare values
EPwm6Regs.CMPA.bit.CMPA = 98; // Set compare A value
EPwm6Regs.CMPB.bit.CMPB = 98; // Set compare B value

// Set actions
EPwm6Regs.AQCTLA.bit.ZRO = AQ_SET;
EPwm6Regs.AQCTLA.bit.CAU = AQ_CLEAR;

EPwm6Regs.AQCTLB.bit.ZRO = AQ_SET;
EPwm6Regs.AQCTLB.bit.CBU = AQ_CLEAR;


EPwm6Regs.AQCSFRC.bit.CSFA = 01; //force low
EPwm6Regs.AQCSFRC.bit.CSFB = 02; //force high as polarity change

EPwm6Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;
EPwm6Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm6Regs.DBCTL.bit.DEDB_MODE = 0;
EPwm6Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm6Regs.DBCTL.bit.HALFCYCLE = 1;

EPwm6Regs.DBRED = 32; //because of halfcycle clocking
EPwm6Regs.DBFED = 32; //because of halfcycle clocking

// Interrupt where we will change the Compare Values
EPwm6Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm6Regs.ETSEL.bit.INTEN = 0; //Disable INT
EPwm6Regs.ETPS.bit.INTPRD = ET_DISABLE; //Generate INT on 3rd event
EPwm6Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group
EPwm6Regs.ETSEL.bit.SOCASEL = 1; // Select SOC on up-count
EPwm6Regs.ETPS.bit.SOCAPRD = 3;

/////////////////////High Resolution PWM//////////////
EALLOW;
EPwm6Regs.HRCNFG.all = 0x0;

EPwm6Regs.HRCNFG.bit.EDGMODE = 2; // MEP control on falling edge
EPwm6Regs.HRCNFG.bit.EDGMODEB = 1; // MEP control on rising edge

EPwm6Regs.HRCNFG.bit.CTLMODE = 0; // CMPAHR and TBPRDHR HR control
EPwm6Regs.HRCNFG.bit.CTLMODEB = 0; // CMPAHR and TBPRDHR HR control

EPwm6Regs.HRCNFG.bit.HRLOAD = 1; // load on CTR = TBPRD
EPwm6Regs.HRCNFG.bit.HRLOADB = 1; // load on CTR = TBPRD
//////////
EPwm6Regs.HRPCTL.bit.PWMSYNCSEL = 1;
EPwm6Regs.HRCNFG.bit.AUTOCONV = 0;
EPwm6Regs.HRPCTL.bit.TBPHSHRLOADE = 0;
EPwm6Regs.HRPCTL.bit.HRPE = 1; // Turn on high-resolution period control.
EPwm6Regs.HRMSTEP.bit.HRMSTEP = 28 ; //hrmstep is 180pS 5ns/180ps = 27.77
EDIS;
//////////////////////////////////////////////////////

step 3:
EPwm6Regs.TBCTL.bit.SWFSYNC = 1;

step 4:
EPwm6Regs.AQCSFRC.bit.CSFA = 01; //force low
EPwm6Regs.AQCSFRC.bit.CSFB = 02; //force high

step 5:
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;

step 6:
//Till this stap epwm is configured and force low
//setting appropriate value to generate 1011kHz ,50% duty and 80nS dead band.
//(period and duty both HR, dead band is not HR)
EPwm6Regs.TBPRD = 196;
EPwm6Regs.TBPRDHR = 53760;
EPwm6Regs.CMPA.bit.CMPA = 98;
EPwm6Regs.CMPB.bit.CMPB = 98;
EPwm6Regs.CMPA.bit.CMPAHR = 6656;
EPwm6Regs.CMPB.bit.CMPBHR = 6656;
EPwm6Regs.DBRED = 32; //80nS dead band
EPwm6Regs.DBFED = 32; // 80nS dead band

step 7:
EPwm6Regs.AQCSFRC.bit.CSFA = 00; //no effect
EPwm6Regs.AQCSFRC.bit.CSFB = 00; //no effect

After execution of 7th step, i am getting jitter of 4.5nS on channel B. (I already tried with and without SFO function but problem remains same)

As i think jitter length(4.5nS) is because of following reason,
1011KHz = 989.11nS => 989.11/2 = 494.5 ==> in which 4.5nS is applied through HR

Thanks and Regards,
Maulik Timbadiya

Dear Bharathi,

Thank you for your suggestion and comment. I have taken trial based on your suggestion and concluded below point,

1. If I have disable HRPE bit then there is no meaning of high resolution. Jitter is removed in this case. But, I can not get frequency as programmed. For example, getting 1020kHz instead of 1011kHz.
2. Jitter is only appear in case of when high resolution period needs to add. For example, on same program jitter is not appear when 1000kHz frequency is programmed. Because of CMPAHR/CMPBHR becomes 0. but when I need to load CMPAHR/CMPBHR with certain value at that time only jitter appear.
3. In following code jitter appear on both ePWMA and ePWMB.

Changes :
1. Now PWM module is running on 100MHz.
2. I have turned on auto conversion.
3. SFO function is on continues calling.
4. Dead band module is completely bypassed.

New code based on your suggestion:

EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;

EPwm6Regs.TBCTL.bit.CTRMODE = 0;// Count up
EPwm6Regs.TBPRD = 97;
EPwm6Regs.TBPRDHR = 59648;

EPwm6Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm6Regs.TBCTR = 0x0000; // Clear counter

EPwm6Regs.TBCTL.bit.FREE_SOFT = 3;
EPwm6Regs.TBCTL.bit.PRDLD = 0;
EPwm6Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm6Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm6Regs.TBCTL.bit.SWFSYNC = 0;
EPwm6Regs.TBCTL.bit.SYNCOSEL = 1;
EPwm6Regs.TBCTL.bit.PRDLD = 0;
EPwm6Regs.TBCTL.bit.PHSEN = TB_DISABLE;
// Setup TBCTL2
EPwm6Regs.TBCTL2.bit.SYNCOSELX = 0;
EPwm6Regs.TBCTL2.bit.PRDLDSYNC = 0;

// Setup shadow register load on ZERO
EPwm6Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm6Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm6Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm6Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

// Set Compare values
EPwm6Regs.CMPA.bit.CMPA = 49;
EPwm6Regs.CMPA.bit.CMPAHR = 6400;
EPwm6Regs.CMPB.bit.CMPB = 49;
EPwm6Regs.CMPB.bit.CMPBHR = 6400;

// Set actions
EPwm6Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM1A on Zero
EPwm6Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM1A on event A, up count

EPwm6Regs.AQCTLB.bit.ZRO = AQ_SET;
EPwm6Regs.AQCTLB.bit.CBU = AQ_CLEAR;


EPwm6Regs.AQCSFRC.bit.CSFA = 00;
EPwm6Regs.AQCSFRC.bit.CSFB = 00;

EPwm6Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;
EPwm6Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm6Regs.DBCTL.bit.DEDB_MODE = 0;
EPwm6Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
EPwm6Regs.DBCTL.bit.HALFCYCLE = 0;

EPwm6Regs.DBRED = 32;
EPwm6Regs.DBFED = 32;

/////////////////////High Resolution PWM//////////////
EALLOW;
EPwm6Regs.HRCNFG.all = 0x0;

EPwm6Regs.HRCNFG.bit.EDGMODE = 2;
EPwm6Regs.HRCNFG.bit.EDGMODEB = 2;

EPwm6Regs.HRCNFG.bit.CTLMODE = 0;
EPwm6Regs.HRCNFG.bit.CTLMODEB = 0;

EPwm6Regs.HRCNFG.bit.HRLOAD = 0;
EPwm6Regs.HRCNFG.bit.HRLOADB = 0;
//////////
EPwm6Regs.HRCNFG.bit.AUTOCONV = 1;
EPwm6Regs.HRPCTL.bit.HRPE = 1;
EPwm6Regs.HRMSTEP.bit.HRMSTEP = 56 ; //hrmstep is 180pS 10ns/180ps = 55.55
EDIS;

EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;


Problem still exist. Herewith I have attached waveform which shows fine duty and frequency. But if I zoom then I can see falling edge continuously moving.(I have put trigger on rising edge and continuous monitor falling edge). That movement length is 4.5nS for 1011kHz and 50% duty.

Thanks and regards,
Maulik Timbadiya

Hi Maulik,

As i said earlier - Test to disable HRPE is only for identifying the source of your problem - i understand it's needed for freq. control.
You could still use duty cycle control with high resolution with HRPE disabled.
I do see below code.
EPwm6Regs.HRMSTEP.bit.HRMSTEP = 56 ; //hrmstep is 180pS 10ns/180ps = 55.55
You do not need to write to HRMSTEP since you are calling SFO and AUTOCONV is also enabled.
Please monitor/log the value of HRMSTEP before and after calling SFO over multiple iterations.
Check if there are any abnormalities in the values.

Also, you mentioned that the "4. Dead band module is completely bypassed."
But I do see below in the code.
EPwm6Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
Can you completely disable and check?

-Bharathi.

Dear Bharathi,

By selecting OUT_MODE = 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect.
HRMSTEP = 56 is just as initialization.

I have noticed following things based on previous experiment:
1. Jitter length is depends on PWM clock.(10nS for 100MHz)
2. As datasheet is not recommending but ePWM/HRPWM module can run at 200MHz.

In 200MHz PWM clock case, I am getting 5nS Jitter. Which is better then 10nS.
I will update you as soon as possible for "what will happen if HRPE enable/disable?"

Thanks and Regards,
Maulik Timbadiya

Dear Bharathi,

If I disable HRPE then jitter is removed.

Thanks and Regards,
Maulik Timbadiya

Hi Maulik,

Is it possible to share a test case? Just having HRPE enabled should not result in any jitter.

-Bharathi.

Dear Bharathi,

I am waiting for your response. Problem is still exist.

Regards,
Maulik

Hi,

Is there any update? Problem is still exist.

Do You test last attached example with your system?

Regards,
Maulik

Maulik,

I do not see any issue here. I believe the problem mentioned by you in the other thread regarding duty cycle change on PWMB and this one may be related to some system level issues and/or measurement setup etc.
We can continue the discussion on the other thread.

-Bharathi.