CCS/TMS320F28069: interrupt nesting with the same group (INT3.6 and INT3.7)

user3574588

Part Number: TMS320F28069

Tool/software: Code Composer Studio

I have a interrupt nesting problem with the INT3.6 and INT3.7, the INT3.6 is 500kHz interrupt and INT3.7 is 50kHz interrupt. they both trigger when count == zero and the count is sync.

when these two interrupt overlaping INT3.6 will miss the interrupt. my ISR code are as follow:

__interrupt void epwm6_timer_isr(void)
{

......

EPWM6Regs.ETCLR.bit.INT = EPWM_INT_FLAG_CLEAR;

PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

#if DEBUG_PWM ==1
SCPwmRegs.AQSFRC.bit.OTSFA = 1;
SCPwmRegs.AQSFRC.bit.ACTSFA = 1;
#endif
}

__interrupt void epwm7_timer_isr(void)
{
EINT;
IER&=M_INT3;

........

EPWM7Regs.ETCLR.bit.INT = EPWM_INT_FLAG_CLEAR;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

#if DEBUG_PWM ==1
SLPwmRegs.AQSFRC.bit.OTSFA = 1;
SLPwmRegs.AQSFRC.bit.ACTSFA = 1;
#endif
}

the test picture is follow:

Look forward to your reply.

Thank you.

over 7 years ago

0 Richard Poley over 7 years ago

TI__Mastermind 27200 points

You need to move the writes to PIEACK to the start of each ISR. Further interrupts on that line will not happen until the PIE group is acknowledged.

Also, if you are enabling core interrupts inside an ISR using EINT, you need to disable them again before it ends to protect the context restore. Finally I think the instruction to re-enable INT3 within IER was wrong.

Your 3.7 ISR would look something like this:

__interrupt void epwm7_timer_isr(void)
{
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
IER |= M_INT3;
EINT;

........

EPWM7Regs.ETCLR.bit.INT = EPWM_INT_FLAG_CLEAR;

#if DEBUG_PWM ==1
SLPwmRegs.AQSFRC.bit.OTSFA = 1;
SLPwmRegs.AQSFRC.bit.ACTSFA = 1;
#endif

DINT;
}

Please try this and see if it works.

Regards,

Richard

0 user3574588 over 7 years ago in reply to Richard Poley

Prodigy 80 points

It works . Thank you.

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CCS/TMS320F28069: interrupt nesting with the same group (INT3.6 and INT3.7)