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TMS320F28069: decoupling capacitor for VDDIO

Part Number: TMS320F28069

Hello Champs,

As below description in F2806x datasheet for VDDIO:

Digital I/O and Flash Power Pin. Single supply source when VREG is enabled. Place a 2.2-uF decoupling capacitor on each pin. The exact value of the total decoupling capacitance should be determined by the system voltage regulation solution.

Customer needed to know whether that 2.2-uF is only the nominal value of the decoupling capacitor or that the decoupling capacitor should always be 2.2-uF during all operating temperature range.

Would you please kindly help? Thanks!

Best Regards,

Linda

  • Linda,

                I presume you are looking at SPRS698F, not SPRS698G. The decoupling capacitor value should be chosen based on the application. Critical parameters to consider would be the total load connected to the 3.3v rail (i.e. in addition to the MCU itself), the board layout and the dynamic current requirement of the application.

  • Hello Hareesh,

    Thank you for your reminder. But in SPRS698G, there is below description for VDD and VDDA:

    VDD: CPU and Logic Digital Power Pins. When using internal VREG, place one 1.2-μF capacitor between each VDD pin and ground. Higher value capacitors may be used.
    VDDA: Analog Power Pin. Tie with a 2.2-μF capacitor (typical) close to the pin.

    Customer still needed to know whether that 2.2-uF/1.2uF is only the nominal value of the decoupling capacitor or that the decoupling capacitor should always be 2.2-uF/1.2uF during all operating temperature range.

    Would you please kindly help? Thanks!

    Best Regards,
    Linda
  • Linda,

    The values are nominal.

    -Tommy