• State TI Thinks Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 1 answer
  • Subscribers 81 subscribers
  • Views 1145 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TMS320F28379D: High-resolution period control seems to delay shadow-to-active CMPA value transfer

CCS/TMS320F28335: Different delay in EPWM output rising and falling edges

Archana C M
Prodigy 30 points
Part Number: TMS320F28335

Tool/software: Code Composer Studio

Hi,

I observe that when I'm loading the CMPA register with the desired variable for EPWM comparison, the delay in the falling edge is more than that in the rising edge. The pink line is the variable that I'm feeding to CMP register, it's low value is 0 and high is 1.2*TBPRD. Hence I expect the output waveform of EPWM (yellow) to closely follow the input pink waveform, which I'm displaying using a DAC. The green pulses indicate the zero crossings of TBCTR up down counter, being displayed as the EPWM output by comparing against 0.1*TBPRD.

(please ignore the cursors (dotted vertical lines) in the following figures, by 'delay' I mean the lag between the pink and the yellow waveforms rising/falling')

Rising edge: delay less than one period of TBCTR triangle

Falling edge: delay is one period of TBCTR triangle

Due to this increased delay in the falling pulse in comparison to that of the rising pulse, the width of the output pulses is greater than that of the input variable pulse. This is the case irrespective of whether the shadow is enabled or not.

How do I minimize the delay of the EPWM output pulses, so that the lag between the pink and yellow waveforms is minimized?

How do I ensure that the delay is the same for both edges, so that the pulse widths are unaffected?

Thanks

Archana

  • 0
    TI__Expert 5380 points
    Hi Archana,

    A couple of questions to understand more about this issue you are facing:
    1) When you mention delay of the rising and the falling edges, do you mean to say that these delays are caused due to the configuration of the deadband registers of ePWM? If yes, could you please check out and mention the values you have configured for the Rising Edge Delay(RED) and the Falling Edge Delay(FED).

    2) Could you give more information on what each of the scope waveforms are about? i am not able to understand how the EPWM output should follow the pink waveform closely. If you could give me an example of the ePWM configuration you are using, that would enable me to understand the problem and help you further.

    Thanks & Regards
    Pramod
  • 0 in reply to Pramod P
    Prodigy 30 points

    Hi Pramod,

    I don't think the delay is due to the deadband. I've set 80 for both FED and RED. These are my settings:

    EPwm1Regs.TBPRD = 3901;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0x2; 
EPwm1Regs.TBCTL.bit.CLKDIV = 0x2;
EPwm1Regs.TBPHS.half.TBPHS = 0; 
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; 
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module
EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0;//SHADOW enabled
EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // set actions for EPWM1A AQ_CLEAR
EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm1Regs.DBFED = 80; // FED = 50 TBCLKs
EPwm1Regs.DBRED = 80; // RED = 50 TBCLKs

    I update the value of a variable 's1a' during each iteration. This s1a is being displayed through DAC as the pink waveform. 's1a' toggles between 0 and 1.2
    EPwm1Regs.CMPA.half.CMPA = s1a*EPwm1Regs.TBPRD;
    Since the magnitude of s1a is greater than TBPRD, the output of comparison with TBCTR will also be a square waveform, identical in shape to s1a. A little bit of delay would be tolerable. For me, the issue is that the output pulses have different width from the input s1a pulses due to the unequal rise and fall delays.
    Yellow waveform is the output at the EPWM pin.

  • 0 in reply to Archana C M
    TI__Expert 5380 points
    Hi Archana,

    Looking at your configuration, both the delays (RED and FED) are not going to taking effect on the ePWM output. If it is what you want, you have the deadband configuration incomplete. Try removing the deadband settings and check if you get the same rising and falling edge delays. This will ensure that the problem is with the deadband settings. I still believe this is the cause for your problem.

    Meanwhile, could you please answer the following questions so that i can try and reproduce your scenario at my end:

    1. Check by how much the rising edge and the falling edge delays are differing?
    2. The yellow output is ePWM1A or ePWM1B?
    3. How frequently are you changing the 's1a' variable(Or what is the iteration value)? Is that in any way related to the TBPRD values?

    Thanks & Regards
    Pramod P
  • 0 in reply to Pramod P
    Prodigy 30 points

    Would you please elaborate on why you said the FED and RED would not take effect? How can I ensure that they take effect?

    1. The rising edge and falling edge delay is fixed in terms of TBPRD cycles. When shadow is disabled (1), the delays are as follows:

    Rising edge: about half the up-down period of TBCTR

    Falling edge: about one period of TBCTR up-down

    2. The yellow output is ePWM1A

    3. The delay is observed irrespective of the rate of change of s1a value. I've attached a project, in which the 'archana_EPWM_delay.c' code contains s1a toggling during every iteration of the code (iteration forced by TBCTR zero crossing). Also 's1a' is being displayed through DAC channel D. Zero crossings of TBCTR are being viewed through ePWM2A (green pulses).archana_EPWM_delay.rar

  • 0 in reply to Archana C M
    TI__Expert 5380 points
    Hi Archana,

    Please go through the deadband section from the eTPWM reference guide in the TMS320F28335 product page.

    Figure 31 which explains the operational highlights for the Dead-Band Submodule clearly shows that the EPWMxA in cannot have both RED and FED effects taken in simultaneously.
    Figure 32 demonstrates the various combinations possible and none of these combinations have both RED and FED on the same PWM output. The feature which you are asking (where the RED and FED both have to take effect on the same PWM) is possible in the future devices( TMS320F2837x, TMS320F28004x).

    This is what I am suspecting is the answer to the issue you are facing. Only one of the delays in the Deadband configuration is taking effect in your example, so kindly try removing the deadband configuration from your example and try it out.

    Thanks & Regards
    Pramod P
  • 0 in reply to Archana C M
    TI__Expert 5380 points
    Hi Archana,

    It's been a while since I heard back from you last. Hence I am assuming that you were able to resolve your issue. If this isn't the case, please respond back to this thread. If the thread locks, please make a new thread describing the current status of your issue and I would surely help you on that.

    Thanks & Regards
    Pramod