CORTEX-R4#27
Debug Reset Does Not Reset DBGDSCR When In Standby Mode.
The debug reset input, PRESETDBGn, resets the processor's debug registers as specified in the ARMv7R Architecture. The debug reset is commonly used to set the debug registers to a known state when a debugger is attached to the target processor. When the processor is in Standby Mode and the clock has been gated off, PRESETDBGn fails to reset the Debug Status and Control Register (DBGDSCR).
CORTEX-R4#33
Processor Can Deadlock When Debug Mode Enables Cleared.
The Cortex-R4 processor supports two different debugging modes: Halt-mode and Monitor-mode. Both modes can be disabled. Bits [15:14] in the Debug Status and
Control Register (DBGDSCR) control which, if any, mode is enabled. Additionally, debug events can only occur if the invasive debug enable pin, DBGEN is asserted. Deadlocks
should not occur when the debug mode is changed. Issue If there are active breakpoints or watchpoints at the time when the debugging modes are
disabled via the DBGDSCR or DBGEN, this issue can cause the processor to deadlock (in the case of a breakpoint) or lose data (in the case of a watchpoint).
The move mentioned issues are pertained to Debug mode, so were the workarounds implemented in CCS10.1.1 tool?
>> I will have to check with the debugger team to confirm if these workarounds are implemented in CCS.
The highlighted point is yet to resolve from the previous thread, Did you get chance to discuss with tools team.
