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RM48L940: Flash ECC Test

Intellectual 600 points

Replies: 2

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Part Number: RM48L940

My 1Bit ECC Flash test seems to pass, but it fails 2Bit ECC test using SL_SelfTest_Flash(FLASH_ECC_TEST_MODE_2BIT, 0, &failInfoFlash). In the code segment below the, the condition (BIT(ESM_G3ERR_FMC_UNCORR) == (sl_esmREG->SR1[2] & BIT(ESM_G3ERR_FMC_UNCORR)) evaluates to FALSE and I confirmed that  ESM SR1[2] is not set.

When the line flashread = *(volatile uint32 *)flashBadECC2; is executed, bit 7 of the ESR SR3 is set. The ESM SR3[7] is set as soon as I execute flashread = *(volatile uint32 *)flashBadECC2;

Why is ESM SR1[2] being checked instead of ESM SR3[7]? I thought SR1 is for Group 1 error but 2Bit error will trigger a Group 3 error. Can anyone explain what is going on and what I need to check to get my test to pass?

        sl_flashWREG->FDIAGCTRL |= F021F_FDIAGCTRL_DIAG_TRIG;

        /*SAFETYMCUSW 58 S MR:14.3 <APPROVED> Comment_16*/
        flashread = *(volatile uint32 *)flashBadECC2;

#if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_TMS570LS07x_) || defined(_TMS570LS09x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM44x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
        if ((FLASH_ECC_TEST_MODE_2BIT_FAULT_INJECT != testType)&&(FLASH_ADDRESS_ECC_FAULT_INJECT != testType))
#endif
#if defined(_TMS570LC43x_) || defined(_RM57Lx_)
        if (FLASH_ECC_TEST_MODE_2BIT == testType)
#endif
        {
#if defined(_TMS570LS31x_) || defined(_TMS570LS12x_) || defined(_TMS570LS07x_) || defined(_TMS570LS09x_) || defined(_RM48x_) || defined(_RM46x_) || defined(_RM44x_) || defined(_RM42x_) || defined(_TMS570LS04x_)
            /*SAFETYMCUSW 134 S MR: 12.2 <APPROVED> Comment_5*/
            /*SAFETYMCUSW 134 S MR: 12.2 <APPROVED> Comment_5*/
            /*SAFETYMCUSW 408 S MR:12.4 <APPROVED> Comment_12*/
            /*SAFETYMCUSW 96 S MR: 6.2,10.1,10.2,12.1,12.6 <APPROVED> Comment_25*/
            if ((F021F_FEDACSTATUS_B1_UNC_ERR == (uint32)(sl_flashWREG->FEDACSTATUS & F021F_FEDACSTATUS_B1_UNC_ERR))
                    && (sl_flashWREG->FUNCERRADD == (uint32)0x8u)
                    && (BIT(ESM_G3ERR_FMC_UNCORR) == (sl_esmREG->SR1[2] & BIT(ESM_G3ERR_FMC_UNCORR))))
                sl_flashWREG->FEDACSTATUS = F021F_FEDACSTATUS_B1_UNC_ERR;
                sl_esmREG->SR1[2] = BIT(ESM_G3ERR_FMC_UNCORR);

  • Hello,

    The ESM registers for the group status registers are at address offsets 0x18, 0x1C and 0x20. These are implemented as an array of three 32-bit registers defined as "uint32 SR1[3U];" in the header file sl_regs_esm.h

    So, SR1[2] is the ESMSR3 register for group3 error status flags as described in the TRM.

    Regards,
    Sunil
  • In reply to Sunil Oak:

    Thanks Sunil. This makes sense now. I interpreted SR1 as status register 1.

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