We are using MSP430F6777A chip in one of our meters and are having some issue during Phase calibration. As mentioned in the user manual and 3 Phase Metering application note we are using the DELAYINT register setting to achieve this. The ADC settings for the same are as given below.
|
Register Name
|
Clock Source Select
|
Clock Pre Div
|
Clock Div
|
REF Select
|
Overflow
|
|
Setting
|
SD24SSEL_SMCLK
|
SD24PDIV_4
|
SD24_B_CLOCKDIVIDER_1
|
SD24_B_REF_INTERNAL
|
SD24OV32_On_32
|
ADC Settings Advanced:
|
CH NO
|
CH Description
|
Converter
|
Alignment
|
Start Select
|
Conversion Mode
|
Data Format
|
Sample Delay
|
Over sampling Ratio
|
Gain
|
|
0
|
Current 3rd Channel
|
0
|
SD24ALGN
|
SD24SCS__GROUP0 (0x0008)
|
0x00
|
SD24DF_1
|
SD24INTDLY_0
|
256
|
SD24GAIN_1 (0)
|
|
1
|
Current 2nd Channel
|
1
|
SD24ALGN
|
SD24SCS__GROUP0 (0x0008)
|
0x00
|
SD24DF_1
|
SD24INTDLY_0
|
256
|
SD24GAIN_1 (0)
|
|
2
|
Current 1st Channel
|
2
|
SD24ALGN
|
SD24SCS__GROUP0 (0x0008)
|
0x00
|
SD24DF_1
|
SD24INTDLY_0
|
256
|
SD24GAIN_1 (0)
|
|
3
|
Voltage 3rd Channel
|
3
|
SD24ALGN
|
SD24SCS__GROUP0 (0x0008)
|
0x00
|
SD24DF_1
|
SD24INTDLY_0
|
256
|
SD24GAIN_1 (0)
|
|
4
|
Voltage 2nd Channel
|
4
|
SD24ALGN
|
SD24SCS__GROUP0 (0x0008)
|
0x00
|
SD24DF_1
|
SD24INTDLY_0
|
256
|
SD24GAIN_1 (0)
|
|
5
|
Voltage 1st Channel
|
5
|
SD24ALGN
|
SD24SCS__GROUP0 (0x0008)
|
0x00
|
SD24DF_1
|
SD24INTDLY_0
|
256
|
SD24GAIN_1 (0)
|
|
6
|
Neutral Voltage
|
6
|
SD24ALGN
|
SD24SCS__GROUP0 (0x0008)
|
0x00
|
SD24DF_1
|
SD24INTDLY_0
|
256
|
SD24GAIN_1 (0)
|
Preload Channel and Register Settings:-
|
CH NO
|
CH Description
|
Register Used
|
Load value
|
|
0
|
Current 3rd Channel
|
SD24BPRE0
|
172
|
|
1
|
Current 2nd Channel
|
SD24BPRE1
|
160
|
|
2
|
Current 1st Channel
|
SD24BPRE2
|
158
|
|
3
|
Voltage 3rd Channel
|
SD24BPRE3
|
128
|
|
4
|
Voltage 2nd Channel
|
SD24BPRE4
|
128
|
|
5
|
Voltage 1st Channel
|
SD24BPRE5
|
128
|
|
6
|
Neutral Voltage
|
SD24BPRE6
|
128
|
With Following ADC settings and keeping the ISR empty our ISR gets generated every 164 uSec(as expected). This is without Phase calibration in picture. We tried testing with fixed values in preload register for phase calibration and saw that the interrupt generation shifts from 164 uSec to 136 uSec. Please help us understand if we are missing some thing in setting up the ADC.
NOTE: The default preload value is 128
