MSP430FR6007: Errata PMM32

I assume no. Because it is "And" not "Or".

It looks like the problem lies on the synchronization between CPU and peripheral/ IRQ request

Hi Eason,

As for condition 2, the errata state that the condition is met if SMCLK and MCLK are different frequencies, it does not matter if they are synchronous. Would you kindly clarify if this is correct? 

The customer has a follow-up question bout this. Please see below.

If this is correct, then SMCLK must always have the same frequency as the MCLK. Can this be true?

The 3 first sub-conditions are often met. For example, if the CPU goes to low power after wakened to capture a timer edge on the ACLK. Interrupts can come at any time.
Then only the 4^th sub condition is left. in practice, it means that the 4^th sub-condition must never be met.

Thank you kindly,

Regards,

Marvin

1.MCLK is to CPU and SMCLK is to peripheral. The problem is related to interrupt. So I assume if the MCLK and SMCLK is not synchronous, it will cause the problem. It is my guess based on the information I see on PMM32

2. Yes, SMCLK must always have the same frequency as the MCLK.

Hi Eason.

I am a little confused. I read this as

In number 1. You indicate that we have no problem. (As the clocks are synchronous. SMCLK = MCLK / 4 )

In number 2. You indicate that we have a problem.  

Hi Eason.

Maybe the below can help us.

Our application runs like this:

When the SMCLK is running, LPM1 is entered instead of LPM3.

Interrupts that wake up the CPU from LPM3 does never at the same time, make a peripheral clock request of the SMCLK.

Example: If a UART is idle but ready to receive on high Baud rate, which requires the SMCLK, then LPM1

is used instead of LPM3.

Sorry to make you confused.

1. See from you current setting, you may meet the PMM32 as your interrupt can come at any time.

2. The suggest solution would be making the SMCLK and MCLK to be the same frequency, like 8MHz. Besides, you need to update the UART or other peripherals' clock configuration. For UART, you can check the Table 30-5 Recommended Settings for Typical Crystals and Baud Rates in UG.

OK Eason, thank you for answering.

But wouldn't you say that all designs should be making the SMCLK and MCLK to be the same frequency.

I mean, the first 3 sub conditions are quite normal.

Sorry, I don't quite understand "But wouldn't you say that all designs should be making the SMCLK and MCLK to be the same frequency."

Yes, first 3 sub conditions are quite normal for customers, the way to ensure all the customers not to meet PMM32 is to make the SMCLK and MCLK to be same frequency. I know it means you need to make some change to your code. Maybe another way is to make MCLK to be DCOCLK / 4, if you accept the CPU speed can be slower.