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MSP430G2553: Reg the code logic for trailing edge and leading edge dimming with the timer.

Part Number: MSP430G2553

Hi,

We are working on a no neutral dimmer solution with MSP430G2553 controller. We are facing issues with the dimming control, here we were able to control (dim) the load in trailing edge mode, but unable to control the load in the leading-edge mode. 

We used a timer at 1 MHz frequency and dimming the load with reference to zero cross detection interrupt. 

Logic of Trailing edge dimming:

- Once we receive the ZCD interrupt then turning ON the load for some time between 1 millisecond to 8 milliseconds depends on the dim level. Then starting the timer with the duty value (1000 - 1 millisecond). Once the timer is completed in the timer interrupt, we were turning off the load.

if(P2IFG & BIT3) //Zero cross
{
P2OUT |= BIT1;
P2OUT |= BIT2;

CCR0 = duty; //1000-1 millisecond

P2IFG &= ~BIT3; // P2.3 IFG cleared
}

#pragma vector=TIMER0_A0_VECTOR
__interrupt void Timer_A (void)
{
P2OUT &= ~BIT1; // P1.0 output
P2OUT &= ~BIT2;

CCR0 = 0;
}

For leading-edge dimming, we inversed the IO logic. Turn OFF the load in zero cross and turning ON the load in the timer interrupt. But here the load is turning ON completely and unable to detect the proper zero cross and finally unable control (dim) the load. We did many trials but not succeeded.

Please help to share if there is any code logic available from TI for this type of dimmer solutions. Some of other microcontroller companies have provided sample logics for dimmer solutions.

Please help with the same.

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