I am trying to sample multiple analog channels as mentioned in this post at the end. https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1208935/msp430f6779-msp430f6779-measuring-voltage-of-pwm-signal
I am trying to modify my code to sample multiple analog channels using the DMA example code. However, the DMA ISR triggers, but the code never gets inside the switch statement in bold in the DMA ISR. Also, I commented out the ADC ISR and put that code in the DMA ISR as shown below.
/* Prepare the ADC10A for configuration */
ADC10CTL0 &= ~ADC10ENC;
/* Clear pending interrupts to ensure trigger for DMA */
ADC10IFG = 0;
/* ADC on, ADC10 waits for trigger from the SD24, sampling time 2us 8xADCclk, auto next conv. */
ADC10CTL0 = ADC10SHT0 | ADC10ON | ADC10MSC;
/* Triggered by the SD24, SMCLK/6 = 4MHz, Pulse Sample Mode*/
ADC10CTL1 = ADC10SHP | ADC10SHS_2 | ADC10DIV_0 | ADC10SSEL_0 | ADC10CONSEQ_1; /* Single Channel, Single Conversion */
/* 10-bit conversion results */
ADC10CTL2 |= ADC10RES;
/* Enable ADC conv complete interrupt */
ADC10IE |= ADC10IE0;
/* A3 ADC input select; Vref=AVCC */
ADC10MCTL0 |= ADC10INCH_3 | ADC10SREF_0; // A0,A1,A2,A3(EoS)
/* Start ADC and wait for a software start conversion trigger */
ADC10CTL0 |= ADC10ENC;// + ADC10SC;
// Setup DMA0 (ADC10IFG trigger)
DMACTL0 = DMA0TSEL_24; // ADC10IFG trigger
DMA0SZ = 0x04; // 4 conversions
__data20_write_long((uintptr_t) &DMA0SA, (uintptr_t) &ADC10MEM0); // Source single address
__data20_write_long((uintptr_t) &DMA0DA, (uintptr_t) &ADC_Result[0]); // Destination array address
DMA0CTL = DMADT_4 | DMADSTINCR_3 | DMAEN | DMAIE; // Repeated single transfer, Increment destination, Enable int after seq of convs
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=DMA_VECTOR
__interrupt void DMA0_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(DMA_VECTOR))) DMA0_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch (__even_in_range(DMAIV, 16))
{
case DMAIV_NONE: break; // No interrupts
case DMAIV_DMA0IFG: // DMA0IFG = DMA Channel 0
// sequence of conversions complete
ADC10CTL0 &= ~ADC10ENC;
ADC10CTL1 ^= ADC10ISSH; // Toggle ISSH to provide trigger on each cycle (EQU0)
ADC10CTL0 |= ADC10ENC;
//__bic_SR_register_on_exit(LPM0_bits); // exit LPM0 on return
break;
case DMAIV_DMA1IFG: break; // DMA1IFG = DMA Channel 1
case DMAIV_DMA2IFG: break; // DMA2IFG = DMA Channel 2
case 8: break; // Reserved
case 10: break; // Reserved
case 12: break; // Reserved
case 14: break; // Reserved
case 16: break; // Reserved
default: break;
}
}
