MSP430FR2433: How does the I2C SCL signal work?

Michael Black2

Part Number: MSP430FR2433

Looking at the "eusci_b_i2c_ex3_masterTxMultiple" example, I have a few questions about how the I2C clock signal works.

Here is the code that initializes the I2C module and the SMCLK, which is used to generate the I2C clock signal.

From my understanding, the I2C clock signal is derived from the SMCLK signal in this example (because we designate the SMCLK as the source during the initialization of the I2C module), but we independently initialize both the SMCLK signal and the I2C clock signal, is that correct?

In other words, we go in an set the SMCLK signal frequency to 1MHz, but then when we initialize the I2C module, we set the I2C clock frequency to some other (must be lower) value with the param.dataRate, is that correct?

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    //Set DCO FLL reference = REFO
    CS_initClockSignal(
            CS_FLLREF,
            CS_REFOCLK_SELECT,
            CS_CLOCK_DIVIDER_1
        );
    //Set Ratio and Desired MCLK Frequency and initialize DCO
    CS_initFLLSettle(
            CS_SMCLK_DESIRED_FREQUENCY_IN_KHZ,
            CS_SMCLK_FLLREF_RATIO
            );
    //Set ACLK = VLO with frequency divider of 1
    CS_initClockSignal(
            CS_ACLK,
            CS_VLOCLK_SELECT,
            CS_CLOCK_DIVIDER_1
            );
    //Set SMCLK = DCO with frequency divider of 1
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    //Set DCO FLL reference = REFO
    CS_initClockSignal(
            CS_FLLREF,
            CS_REFOCLK_SELECT,
            CS_CLOCK_DIVIDER_1
        );

    //Set Ratio and Desired MCLK Frequency and initialize DCO
    CS_initFLLSettle(
            CS_SMCLK_DESIRED_FREQUENCY_IN_KHZ,
            CS_SMCLK_FLLREF_RATIO
            );

    //Set ACLK = VLO with frequency divider of 1
    CS_initClockSignal(
            CS_ACLK,
            CS_VLOCLK_SELECT,
            CS_CLOCK_DIVIDER_1
            );

    //Set SMCLK = DCO with frequency divider of 1
    CS_initClockSignal(
            CS_SMCLK,
            CS_DCOCLKDIV_SELECT,
            CS_CLOCK_DIVIDER_1
            );

    //Set MCLK = DCO with frequency divider of 1
    CS_initClockSignal(
            CS_MCLK,
            CS_DCOCLKDIV_SELECT,
            CS_CLOCK_DIVIDER_1
            );

    // Configure Pins for I2C
    GPIO_setAsPeripheralModuleFunctionInputPin(
        GPIO_PORT_UCB0SCL,
        GPIO_PIN_UCB0SCL,
        GPIO_FUNCTION_UCB0SCL
    );
    GPIO_setAsPeripheralModuleFunctionInputPin(
        GPIO_PORT_UCB0SDA,
        GPIO_PIN_UCB0SDA,
        GPIO_FUNCTION_UCB0SDA
    );

    /*
     * Disable the GPIO power-on default high-impedance mode to activate
     * previously configured port settings
     */
    PMM_unlockLPM5();

    EUSCI_B_I2C_initMasterParam param = {0};
    param.selectClockSource = EUSCI_B_I2C_CLOCKSOURCE_SMCLK;
    param.i2cClk = CS_getSMCLK();
    param.dataRate = EUSCI_B_I2C_SET_DATA_RATE_100KBPS;
    param.byteCounterThreshold = 0;
    param.autoSTOPGeneration = EUSCI_B_I2C_NO_AUTO_STOP;
    EUSCI_B_I2C_initMaster(EUSCI_B0_BASE, &param);

over 2 years ago

+1 Bruce McKenney over 2 years ago

Guru 95150 points

Yes. SMCLK is routinely used for many peripherals, so you want to be conscious of what speed it's running at.

The I2C clock (really the EUSCI clock -- it's the same for UART and SPI) is divided down from the source clock (in your case SMCLK) using the integer divisor in the BRW register. The driverlib call makes it appear you can set any (I2C) clock speed you choose, but you can only get integer quotients of SMCLK.

driverlib computes BRW by dividing i2cClock/dataRate; last I looked it did a truncating division, so if it doesn't divide evenly the clock runs faster than you asked for. (1MHz/100kHz is fine, but 1MHz/400kHz results in 500kHz.)

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MSP430FR2433: How does the I2C SCL signal work?