MSP430FR2476: Unable to add timers and interrupts in BSL Code

Hi Team,

I have successfully flashed the LED code to MSP430FR2476(target) with MSP430FR2311(Host) with reference MSP430FRBoot – Main Memory Bootloader and Over-the-Air Updates for MSP430 FRAM Large Memory Model Devices and User’s Guide MSP430 FRAM Devices Bootloader (BSL). But additional watchdog interrupt or Timer interrupt isn't getting initialized i tried debugging and adding breakpoint after WDT initialization
Any suggestions.
Below is the main file where i tried adding the WDT interrupt

#include "msp430.h"
#include "TI_MSPBoot_Common.h"
#include "TI_MSPBoot_CI.h"
#include "TI_MSPBoot_MI.h"
#include "TI_MSPBoot_AppMgr.h"

unsigned int *program_counter=NULL ;

//
// Local function prototypes
//

void Software_Trim(); // Software Trim to get the best DCOFTRIM value
#define MCLK_FREQ_MHZ 8 // MCLK = 8MHz

static void clock_init(void);

char JmpToApp;

void main_boot(void)
{
// Stop watchdog timer to prevent time out reset
WDTCTL = WDT_ADLY_1000;
SFRIE1 |= WDTIE;

// WDTCTL = WDTPW + WDTHOLD;

P4DIR |= BIT7;

PM5CTL0 &= ~LOCKLPM5;
clock_init();

if (JmpToApp == 1)
{
__disable_interrupt();
((void (*)()) 0xC402)();
}
// Validate the application and jump if needed
if (TI_MSPBoot_AppMgr_ValidateApp() == TRUE_t)
TI_MSPBoot_APPMGR_JUMPTOAPP();

TI_MSPBoot_CI_Init(); // Initialize the Communication Interface

__bis_SR_register(GIE);

while (1)
{

// Poll PHY and Data Link interface for new packets
TI_MSPBoot_CI_PHYDL_Poll();

// If a new packet is detected, process it
if (TI_MSPBoot_CI_Process() == RET_JUMP_TO_APP)
{

// If Packet indicates a jump to App
JmpToApp = 1;

TI_MSPBoot_AppMgr_JumpToApp();

}

}

}

#pragma vector = WDT_VECTOR
__interrupt void WDT_ISR(void)
{
P4OUT ^= BIT7;
}

/******************************************************************************
*
* @brief Initializes the MSP430 Clock
*
* @return none
*****************************************************************************/
//inline static void clock_init(void)
static void clock_init(void)
{
CSCTL1 = DCOFTRIMEN | DCOFTRIM0 | DCOFTRIM1 | DCORSEL_3; // Set DCO = 8Mhz
CSCTL2 = FLLD_0 + 243; // DCODIV = 8MHz
__delay_cycles(3);
__bic_SR_register(SCG0); // enable FLL
//Software_Trim(); // Software Trim to get the best DCOFTRIM value
CSCTL4 = SELA__REFOCLK + SELMS__DCOCLKDIV; // set ACLK = VLO
// MCLK=SMCLK=DC

#if (MCLK==1000000)
CSCTL5 = DIVS__8 + DIVM__8; // Divide DCO/8
#elif (MCLK==4000000)
CSCTL5 = DIVS__2 + DIVM__2; // Divide DCO/2
#elif (MCLK==8000000)
CSCTL5 = DIVS__1 + DIVM__1; // Divide DCO/1
#else
#error "Please define a valid MCLK or add configuration"
#endif

}

Regards,

Pallavi