MSP430F6779A: about deviation of start-up MCLK and SMCLK 1.048576 MHz

Part Number: MSP430F6779A

Tool/software:

as the default start-up MCLK and SMCLK to 1.048576 MHz

so, in first start up the MCLK and SMCLK should not settle to 1.048576 MHz (need wait settle time).

Is there any error specification of SMCLK during this time (e.g. - 20%)?

Because this SMCLK also use for watchdog at first start up (may not 31.2 ms as the clock deviation)

  • Hi, 

    According to the datasheet, we do not provide data for this part, please test it yourself.

    Regards,

    Helic

  • The datasheet does have enough information to make an estimate:

    1) At Reset, DCORSEL=2,DCO=0,MCO=0 [Ref UG (SLAU208Q) Tables 5-3/-4]

    2) fDCO(2,0) is somewhere between 320kHz and 750kHz [Ref datasheet (SLAS982A) Table 5-5]

    3) Each DCO step is (ratio sDCO) between 1.02 and 1.12 [Ref datasheet Table 5-5]

    4) Every 32 REFCLK ticks (~1ms), the DCO steps by 1. [Ref UG Sec 5.2.7, quoted above]

    fDCO()/sDCO vary by device/temperature/voltage, so no one (not even TI) knows beyond the above.

    This also doesn't include the REFCLK startup -- the REFO is spec-ed at 25us (typ.) [datasheet Table 5-4]; a 32kHz crystal can take multiple seconds if it gets cold.

    But this should be enough to construct a spreadsheet for worst-case/best-case to estimate when SMCLK will be "good enough".

    [Edit: Minor notation fix]

  • Hello, thank you. Does that mean 320 khz is the minimum?

    7
  • That's what I see in Table 5.5. I suppose it was measured/characterized at some extreme of voltage/temperature.

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