MSP430F6779A: about deviation of start-up MCLK and SMCLK 1.048576 MHz

The datasheet does have enough information to make an estimate:

1) At Reset, DCORSEL=2,DCO=0,MCO=0 [Ref UG (SLAU208Q) Tables 5-3/-4]

2) fDCO(2,0) is somewhere between 320kHz and 750kHz [Ref datasheet (SLAS982A) Table 5-5]

3) Each DCO step is (ratio sDCO) between 1.02 and 1.12 [Ref datasheet Table 5-5]

4) Every 32 REFCLK ticks (~1ms), the DCO steps by 1. [Ref UG Sec 5.2.7, quoted above]

fDCO()/sDCO vary by device/temperature/voltage, so no one (not even TI) knows beyond the above.

This also doesn't include the REFCLK startup -- the REFO is spec-ed at 25us (typ.) [datasheet Table 5-4]; a 32kHz crystal can take multiple seconds if it gets cold.

But this should be enough to construct a spreadsheet for worst-case/best-case to estimate when SMCLK will be "good enough".

[Edit: Minor notation fix]

Hello, thank you. Does that mean 320 khz is the minimum?

Bruce McKenney47378 said:

7

That's what I see in Table 5.5. I suppose it was measured/characterized at some extreme of voltage/temperature.