Tool/software:
We are interfacing PCF8563 with msp430fr6928 using I2C Communication ,but I2C interrupt is not generated. Here attaching the code snippets for ref and please correct me to move forward .
void fnInitRTC()
{
// RTCCTL0_H = RTCKEY_H; // Unlock RTC_C module
P3SEL0 |= BIT1 | BIT2;
P3SEL1 &= ~(BIT1 | BIT2);
P3DIR |=BIT0;
P3OUT &=~(BIT0);
PM5CTL0 &= ~LOCKLPM5;
UCB1CTLW0 = UCSWRST; // Enable SW reset
UCB1CTLW0 |= UCMODE_3 | UCMST | UCSSEL__SMCLK | UCSYNC; // I2C master mode, SMCLK
UCB1BRW = 160; // fSCL = SMCLK/160 = ~100kHz
UCB1I2CSA = 0xA2; // Slave Address
UCB1CTLW0 &= ~UCSWRST; // Clear SW reset, resume operation
UCB1IE |= UCNACKIE;
data=0x00;
I2C_Master_WriteReg(RTC_WR_ADDR,CTRL1, &data,1);
//__delay_cycles(5500);
data=0x12;
I2C_Master_WriteReg(RTC_WR_ADDR,CTRL2,&data ,1);
// __delay_cycles(5500);
data=0x01;
I2C_Master_WriteReg(RTC_WR_ADDR,MINA,&data ,1);
//__delay_cycles(5500);
data=0x80;
I2C_Master_WriteReg(RTC_WR_ADDR,HRSA, &data,1);
//__delay_cycles(5500);
data=0x80;
I2C_Master_WriteReg(RTC_WR_ADDR,DAYA, &data,1);
// __delay_cycles(5500);
data=0x80;
I2C_Master_WriteReg(RTC_WR_ADDR,WEKA,&data ,1);
__delay_cycles(5500);
data=0x82;
I2C_Master_WriteReg(RTC_WR_ADDR,CLK,&data,1);
__delay_cycles(5500);
data=0x00;
I2C_Master_WriteReg(RTC_WR_ADDR,TIMER,&data,1);
__delay_cycles(5500);
data=0x01;
I2C_Master_WriteReg(RTC_WR_ADDR,TIMERV,&data,1);
__delay_cycles(5500);
}
void I2C_Master_WriteReg(unsigned char dev_addr,unsigned int reg_addr, unsigned char *reg_data, unsigned char count)
//I2C_Mode I2C_Master_WriteReg(uint8_t dev_addr, uint8_t reg_addr, uint8_t *reg_data, uint8_t count)
{
UCB1I2CSA = dev_addr;
UCB1IFG &= ~(UCTXIFG + UCRXIFG); // Clear any pending interrupts
UCB1IE &= ~UCRXIE; // Disable RX interrupt
UCB1IE |= UCTXIE; // Enable TX interrupt
UCB1CTLW0 |= UCTR + UCTXSTT; // I2C TX, start condition
__enable_interrupt();
__bis_SR_register(LPM0_bits + GIE);
__no_operation();
}
void I2C_Master_ReadReg(unsigned char dev_addr,unsigned char reg_addr,unsigned char count)
{
/* Initialize slave address and interrupts */
UCB1I2CSA = dev_addr;
UCB1IFG &= ~(UCTXIFG + UCRXIFG); // Clear any pending interrupts
UCB1IE &= ~UCRXIE; // Disable RX interrupt
UCB1IE |= UCTXIE; // Enable TX interrupt
UCB1CTLW0 |= UCTR + UCTXSTT; // I2C TX, start condition
__enable_interrupt();
__bis_SR_register(LPM0_bits /*+ GIE*/);
}
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = USCI_B1_VECTOR
__interrupt void USCI_B1_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_B0_VECTOR))) USCI_B1_ISR (void)
#else
#error Compiler not supported!
#endif
//Must read from UCB2RXBUF
{
//putch('B');
unsigned char rx_val = 0;
switch(__even_in_range(UCB1IV, USCI_I2C_UCBIT9IFG))
{
case USCI_NONE: break; // Vector 0: No interrupts
case USCI_I2C_UCALIFG: break; // Vector 2: ALIFG
case USCI_I2C_UCNACKIFG: // Vector 4: NACKIFG
// UCB1CTLW0 |= UCTXSTT; // resend start if NACK
break;
case USCI_I2C_UCSTTIFG: break; // Vector 6: STTIFG
case USCI_I2C_UCSTPIFG: break; // Vector 8: STPIFG
case USCI_I2C_UCRXIFG3: break; // Vector 10: RXIFG3
case USCI_I2C_UCTXIFG3: break; // Vector 12: TXIFG3
case USCI_I2C_UCRXIFG2: break; // Vector 14: RXIFG2
case USCI_I2C_UCTXIFG2: break; // Vector 16: TXIFG2
case USCI_I2C_UCRXIFG1: break; // Vector 18: RXIFG1
case USCI_I2C_UCTXIFG1: break; // Vector 20: TXIFG1
case USCI_I2C_UCRXIFG0:
// Vector 22: RXIFG0
rx_val = UCB1RXBUF;
if (RXByteCtr)
{
ReceiveBuffer[ReceiveIndex++] = rx_val;
RXByteCtr--;
}
if (RXByteCtr == 1)
{
UCB1CTLW0 |= UCTXSTP;
}
else if (RXByteCtr == 0)
{
UCB1IE &= ~UCRXIE;
MasterMode = IDLE_MODE;
__bic_SR_register_on_exit(CPUOFF); // Exit LPM0
}
break;
case USCI_I2C_UCTXIFG0:
if (TXByteCtr) // Check TX byte counter
{
UCB1TXBUF = TransmitBuffer[TransmitIndex++]; //TXData[SlaveFlag]; // Load TX buffer
TXByteCtr--; // Decrement TX byte counter
}
else
{
UCB1CTLW0 |= UCTXSTP; // I2C stop condition
UCB1IFG &= ~UCTXIFG; // Clear USCI_B0 TX int flag
__bic_SR_register_on_exit(LPM0_bits); // Exit LPM0
}
break;
default: break;
}
}