Tool/software:
Hi,
I would like to ask there is an example where is set dco to 8 MHz and in the UCSCTL2 register there is also set FLLD_2. In UCSCTL is set SELM_DCOCLK and SELS_DCOCLK and SELA_REF0CLK. Is there any reason to set FLLD_2 in that register when DCOCLKDIV is not set to any clock? And also is safe to use 8 MHz with mclk modul without divider ? I mean without any modification of PMM and also can 8 MHz damaged any modul when connected to MCLK without divider ? I have found the recommended setting in datasheet where it states that PMMCOREVx = 0 to max 8 MHz and also I did not noticed any information about restrictions to frequency that are powered by mclk by default. So I just wanna be sure some of the resources states that caution is required when setting the frequency for mclk. I also set DCO and DCOCLKDIV to 8 MHz with FLLD_0 and it looks like nothing changed like device works normally.
