Tool/software:
Hi team!
I've been testing the SD24 in MSP430AFE253, and trying to use in an application which requires to fetch an approximately 0.08 mV signal with msp. However during my test, neither using the channel 7(which is short-circuit internally) nor pasting both pins in an tin ball could make the output stable. It seems that sampling with SD24 is always mixed with a noise of approximate 0.1 mV Vp-Vp.
My question is, is it unavoidable?(which means a few bits of the LSB are meaningless) Or does the changing data actually reflects the voltage on the short-circult pins? Or are they produced because of the ADC's sampling logic itself? What should I do to reduce the noise(if they are really NOISE)?
FYI, fm=921.6kHz, OSR=256, fs = 3.6kHz. Setting high impedance input buffer on or off may have little influence on the Vp-Vp voltage, but none of them could fix the restless data.
fig.1 data collected during about 4 s.
fig.2 data zoomed in focusing on a duration of 0.2 s.
Thanks for any help!
Best regards,
Ceiliusion
Sigma Delta ADCs always have noise. They are designed that way.
It starts with a really horrible ADC with horrific quantization noise. Single bit! Then jumps through hoops to turn that into something resembling a useful value. The noise is reduced but not eliminated.
Sure! Thank you for your reply. Now I understand why SD ADC have a significant error at the start.
But after some time, with loops continue for a long time(for example, 2s as represented in fig 2), ADC still produce a quantity of noise. Can I use that result (not filtered) to give a conclusion that in my sample circuit, such unsteadily voltage change DOES happen there?
Yours sincerely still confused,
Ceiliusion
There is always noise that the decimation filter doesn't remove so some number of least significant bits will be noise.
Hello Jinqi,
Maybe you have not seen David's latest response. I don't why it is not shown out in this post but I have seen his response through my mailbox. I can convey his response to you. I have read it and I think he is right.
How delta-sigma ADCs work, Part 1 (Rev. A)
There is always noise that the decimation filter doesn't remove so some number of least significant bits will be noise.
Best Regards,
Janz Bai
I did see his reply and his attatchment. Also thanks for your help Janz! btw, is msp430afe designed to have a few invalid bit in its result?
I think David has explained this question very detailed. It is about the Sigma Delta ADC itself.
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