Has anyone used the clock system on the new Wolverine sample chip? I have got my MCLK / SMCLK running at 8 MHz successfully, but the crystal for ACLK appears to be running at 38.4 kHz on my oscilloscope. I am not sure whether is my soldering job or the code that is the problem. I put two 10pF capacitors on the MSP-TS430RGZ48C at C1 and C2 but that didn't make any difference. The crystal is on Q1.
#include <msp430.h>
/*
* Example program for MSP430FR5969 with 32768 Hz Crystal attached.
* Runs at ~8 MHz MCLK/SMCLK and 32768 Hz ACLK
*/
void main()
{
/*
* Clock setup
*/
WDTCTL = WDTPW | WDTHOLD; // Watchdog off
PJSEL0 |= BIT4 | BIT5; // Crystal mode for PJ.4 and .5
CSCTL0 = CSKEY; // Unlock clock registers
CSCTL1 = BIT2 | BIT3; // 8 MHz DCO (8 MHz is FRAM speed limit)
CSCTL3 = 0; // No dividers
CSCTL4 = BIT3 | BIT4; // Disable VLO, LXFTBYPASS on (external pin), lower "drives"
CSCTL0_H = 0xFF; // Lock clock registers
/*
* Test points for clock frequency
*/
P2DIR |= BIT0; P2SEL0 |= BIT0; P2SEL1 |= BIT0; // ACLK on P2.0
P3DIR |= BIT4; P3SEL1 |= BIT4; // SMCLK on P3.4
/*
* Enable onboard LED
*/
P1OUT |= BIT0;
P1DIR |= BIT0;
while (1)
;
}
