Setting up basic clock system, ACLK and MCLK

You shall read product webpage, http://www.ti.com/product/msp430g2553

there you will find x2xx series User's Guide, http://www.ti.com/litv/pdf/slau144j

there you shall read chapter "Basic Clock Module+".

If after reading you still have questions - you are welcome back :)

Hi Rachel,

the clock system is way more complex than on other MCUs because it is so highly configurable, even at runtime.

By default, MCLK (which drives the CPU and the DMA) and SMCLK (used for peripherals, usually synchronous to MCLK) are driven by the internal digitally controlled RC-oscillator (DCO). Its default frequency has a large tolerance. Most 2x family MSPs provide some empirically determined calibration values for a few specific frequencies.
ACLK (auxiliary clock) is usually used for a low-frequency clock signal. The typical use is to source ACLK by a 32kHz watch crystal for RTC purposes or other precision (but low frequency) timing. If there is no crystal, some MSPs offer a fallback to a low-frequency oscillator (VLO) which is 'something that oscillates' (with an unknown frequency in the range of 8-20kHz).

If you don't do anything, the MSP will work. ACLK will be 0Hz or (if available) what the VLO gives. MCLK and SMCLK will be somewhere in the range of ~1MHz. If that's fine for you, then you're done.
If you want to use an external crystal, you'll have to wait until it come sup, and clear its fault flag. The default settings are set for use of a watch crystal anyway, so no need to clear XTS or such.
Things get a bit more complicated if you want to configure the MSP for lowest power consumption. Then some reconfigurations beyond the default are required. Or if you want to use something else than a watch crystal (well, the G2553 only supports a low-frequency watch crystal, so you don't have too many options here)

I also recommend reading the clock system chapter of the users guide. This and at least the first parts of the CPU chapter are mandatory. Then read about digital I/O (especially about the module selection) before proceeding to any other modules like timer or ADC.

Thanks for the info!

Jean, are you saying that I don't need BCSCTL1 &= ~XTS because XTS is by default turned off? Is BCSCTL3 |= LFXT1S_2; necessary or does it default to VLO?

I looked at page 15 of msp430g2553 datasheet on calibration tags. I am not sure how to read this or how to use the information. For DCO, can I select different frequencies (CAL_DCO_1MHZ vs. CAL_DCO_8MHZ).? Is this related to setting the DCO frequencies (page 29). What's the default for RSELx, DCOx and MODx? If I want to change these values to calibrate the DCO frequency how do I do that? For example, if I want to set the frequency to 0.15 MHz (RSELx = 1, DCOx = 3, MODx = 0) do I set:

DCOCTL |= DCO3

Do I set RSEL1 in BCSCTL?

Rachel Gilbert said:

Jean, are you saying that I don't need BCSCTL1 &= ~XTS because XTS is by default turned off?

Actually, the G series does not support high-speed crystals at all, so the bit is a don't care anyway. (see footnote on the register description in the users guide)

Rachel Gilbert said:

Is BCSCTL3 |= LFXT1S_2; necessary or does it default to VLO?

On 2x family, it is necessary. The default is XT! as source for ACLK and when there is no crystal running, ACLK will be 0Hz.
On 5x family, if there is no XT1 crystal attached, ACLK will be automatically sourced by the REFO (a calibrated 32kHz version of the VLO), but a crystal error will be flagged anyway.

Rachel Gilbert said:

For DCO, can I select different frequencies (CAL_DCO_1MHZ vs. CAL_DCO_8MHZ).? Is this related to setting the DCO frequencies (page 29).

Yes. The stored values are just empirically determined settings for the DCO that result in the named frequencies (as close as possible, and with some jitter - caused by how the DCO works)
Simply copy the two values for the desired frequency to BCSCTL1 and DCOCTL and you're done. Be sure that the values haven't been erased (are != 0xff). This would crash the MSP due to overclocking.
Note that the values have been generated for 30°C and VCC=3V. Since the DCO is sensitive to temperature and voltage changes, they only fit best for exactly these conditions. (see tolerances for whole temperature/voltage range in the datasheet)
Any other frequency is possible (well, not any, but a wide range) and you can change it at any time. Yet without a reference to compare what you got, you don't know what a specific setting produces. You only know the range in which it will be (from the datasheet table)

Rachel Gilbert said:

What's the default for RSELx, DCOx and MODx?

See the users guide for register default values. The default results in a DCO frequency somewhere around 1MHz. (0.8..1.5MHz)

Rachel Gilbert said:

If I want to change these values to calibrate the DCO frequency how do I do that? For example, if I want to set the frequency to 0.15 MHz (RSELx = 1, DCOx = 3, MODx = 0) do I set:
DCOCTL |= DCO3
Do I set RSEL1 in BCSCTL?

Unfortunately it's not that easy.  First, the DCOx files has only 3 bits, 0-2, so there is no DCO3 bit. I guess you meant DCO_3 (which corresponds to DCO0|DCO1).
Then you cannot simply use |= on a bitfield. It will set all bits of DCO_3 but won't clear any bits already set (like DCO2) and the result might be not what you expect.

However, setting DCOx=3, MODx=0 and RSELx = 1 will result in typically 150kHz DCO clock speed, but 'typical' doe snot mean 'granted'. As you can see on the other setting sin the table, the upper and lower limit give a large frequency span. Even for those settings where only a typical value is listed.
(I guess, the table is incomplete because there haven't been enough devices tested to give a complete picture - remember that the G series is low-cost)

The 'secure' way is to compare the frequency output of the DCO with a known frequency source. There's a calibration software available that compares the DCO output to the 32768Hz of a watch crystal (or an external precision 32768Hz clock input) to determine the actual DCO frequency - and adjust the DCO until it matches the wanted result. The 4x and 5x family do this in hardware (FLL - frequency-locked-loop). On 2x family, this is done with a timer that counts DCO pulses and triggers on a reference clock pulse, and some software that calculates the required adjustments.

Jens-Michael Gross said:

However, setting DCOx=3, MODx=0 and RSELx = 1 will result in typically 150kHz DCO clock speed, but 'typical' doe snot mean 'granted'.

Other option would be to run DCO at 1MHz factory-calibrated settings and use /8 clock divider, resulting in 0.125MHz. Note that ACLK, MCLK and SMCLK of G-series and 2-series have 1, 2, 4, 8 clock divider options.