Hello,
The short version:
Is timer A considered synchronised to CPU if it is sourced from SMCLK with the input divider set to 2, or does it need to be exactly synchronised to the CPU?
The long version:
I'm implementing a fix for the DCO drift errata bug present in MSP430 and CC430. Here is some pseudo code of what I do:
bool dcoStable = false; // Setup timer A0 in continuous mode, SMCLK/2 timerSetup(); while (true) { disableInterrupts(); if (dcoStable) { dcoStable = false; sleepAndEnableInterrupts(); TA0CCR4 = TA0R + DCO_DRIFT_FIX_TICKS; TA0CTL4 &= ~CCIFG; TA0CTL4 |= CCIE; } else { enableInterrupts(); } } void TIMER0_A1_VECTOR(void) { dcoStable = true; TA0CTL4 &= ~(CCIE | CCIFG); }
I'm worried that my read from TA0R might be unpredictable. Unfortunately I can only use 1 CCR register (all other are already occupied) and I don't want to mess up the timing by stopping timer A.
To put it differently:
Can I safely read TA0R if timer A is sourced from SMCLK/2?
Will I have a problem with propagation delays in the timer divider or counter?