ACLK slows to a crawl during debug

Matt Denoncour78

Other Parts Discussed in Thread: MSP430G2955, MSP-TS430DA38

Hello, I'm using a MSP430G2955 in a MSP-TS430DA38 with a 32.768 crystal. I have the program using the using the using the crystal to generate the ACLK and the DCO generating the MCLK and SMCLK at 8Mhz. I am outputting the ACLK on P2.0 and I can see it starts up just fine when I don't have the debugger on. As soon as I try to debug the ACLK slows way down inconsistently (sometimes 1kHz, sometimes 70Hz). I'm using Code Composer Studio 6.1.3.00033 and an old MSP-FET430UIF. I feel like I have the configuration correct because the ACLK starts up reliably if I cycle power but don't run the debugger. Any ideas what this might be?

over 8 years ago

0 old_cow_yellow over 8 years ago

Guru 58965 points

It may be caused by PCB layout and noise. Do not use debugger and keep watching P2.0 while move your finger close to the crystal.

0 Matt Denoncour78 over 8 years ago in reply to old_cow_yellow

Prodigy 40 points

I had tried this before but only touched the crystal and it didn't reproduce the issue only seemed to change the duty cycle. However I tried it this morning and touched between the ZIF socket and the crystal and the problem reared its head. I will try another crystal and see if that helps. I didn't expect this kind of a problem since I'm using an evm (MSP-TS430DA38).

Thanks,
Matt

0 old_cow_yellow over 8 years ago in reply to Matt Denoncour78

Guru 58965 points

TI has an application note somewhere that talks about how to do PCB layout around the watch crystal. This include very short traces, ground island, etc. A socket is defiantly a no-no.

0 Matt Denoncour78 over 8 years ago in reply to old_cow_yellow

Prodigy 40 points

I hope I don't sound rude but I understand all of that however as I indicated this is a TI supplied EVM which is intended to support the crystal, so I would hope that they evaluated all of their own specifications. When I do commit this to my own board I will certainly tighten up the crystal layout.

0 old_cow_yellow over 8 years ago in reply to Matt Denoncour78

Guru 58965 points

May be someone from TI could help you to work around this problem.

For example, Ryan Brown1 has been very helpful.

0 Matt Denoncour78 over 8 years ago in reply to Matt Denoncour78

Prodigy 40 points

I found this which tells me the internal oscillator cap sizes are very misleading and may be contributing to my problem: http://www.ti.com/lit/ml/slaa367/slaa367.pdf It says that using a 5.5pF setting on the MSP430x2xxx family gives an equivalent Cl of 9pF which exceeds the 6pF spec of the crystal I'm using pretty significantly.

0 Ryan Brown1 over 8 years ago in reply to Matt Denoncour78

TI__Guru**** 204827 points

Hi Matt,

Here is the app report OCY referred to previously: www.ti.com/.../slaa322b.pdf
This issue is definitely related to the load caps. Personally I recommend using external load caps as compared to the internal ones, like you've already seen the XCAP settings result in a higher load capacitance than expected. It's always good to keep the following equation in mind: C1, C2 = 2(CL – Cstray) where CL is defined by the crystal spec and Cstray ranges from 2 to 5 pF due to stray capacitance in your system (traces, pins, device, etc). To improve your system try using XCAPx = 0 and appropriate external capacitors on the XIN and XOUT pins tied to GND.

Regards,
Ryan

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ACLK slows to a crawl during debug